In this paper a 130 nm BCD technology platform is presented. The process offers logic-
devices, flash-devices and high voltage devices with rated voltages up to 60 V. There are …

Conventional modeling methods for ESD protection can be specific to device types or
cannot reproduce the self-heating effect. This work proposes a straightforward modeling …

A simple modification to the lateral DMOS is demonstrated, enabling a significant extension
to the electrical safe operating region. This approach uses a novel Hybrid Source to …

In this paper, approaches for the modeling and simulation of thermal destruction of ICs due
to ESD are discussed from a system point of view. Considered systems consist of ESD …

Large power MOS transistors (bigMOS) have potential electrostatic discharge (ESD)
protection capabilities and are often used in actively controlled ESD clamps. In high-voltage …

Electrostatic discharge (ESD) protection design and characterization with consideration of
harmful electromagnetic compatibility (EMC) events for automotive interface networks are …

A-novel predictive design frame work based on physical principles to predict the ESD
performance of high voltage device is reported. The device It2 is proportional to the critical …

ESD protected LDMOS transistors show sensitivity to voltage overshoots. The pn-diode,
nLDMOS and the combination are investigated in detail. The unique failure mode is …

In high-voltage and especially automotive applications ranging typically from 10 to 100V
operation voltage, statically triggered active ESD clamps are often used due to their false …

This paper investigates a method to increase the holding voltage in a conventional Silicon
Controlled Rectifier (SCR) for ESD power clamping. Specifically, a SCR-LDMOS device with …