[PDF][PDF] Power Optimization of Binary Multiplier Based on FPGA

FT Nasser, IA Hashim - Engineering and Technology Journal, 2021 - iasj.net
In recent years, low power design of digital systems has become one of the vital concerns in
the VLSI design. The primary concerns of VLSI designers are performance, area, reliability …

Power Optimization of KNN Algorithm Based on FPGA

FT Naser, SN Hadi, IA Hashim - 2021 4th International Iraqi …, 2021 - ieeexplore.ieee.org
In modern Field Programmable Gate Array (FPGA) digital systems, power dissipation has
become a critical concern to design digital systems. As size shrinks and density increases in …

Leakage reduction of water distribution network system based on the observation data of water leakage and pressure of actual water distribution network system

P Cheng - Journal of Physics: Conference Series, 2021 - iopscience.iop.org
As the main way of urban water use, water supply system is an important urban
infrastructure. It plays an important role in guaranteeing people's life and economic …

Comparative analysis of low power leakage techniques implemented in different CMOS VLSI Circuits

K Annamma, S Saxena, GS Patel - … International Conference on …, 2022 - ieeexplore.ieee.org
Scaling is necessary with the advancement of technology in VLSI circuits. With scaling
increment in sub-threshold leakage current by minimizing the threshold voltage …

Non-Dynamic Power Reduction Techniques for Digital VLSI Circuits: Classification and Review

A Kumari, V Pandey - 2020 International Conference on …, 2020 - ieeexplore.ieee.org
This paper reviews different methods to reduce the power leakage in dynamic digital circuits
while sustaining the previous logic state. The transistor length has continuously been …

[引用][C] Variation of power and delay in digital CMOS circuit design in DSM Technology

P Praveen, A Zahid - International Journal of Engineering Trends and …, 2017