Over the past decade, system-on-chip (SoC) designs have evolved to address the ever
increasing complexity of applications, fueled by the era of digital convergence …

Future inter-and intra-ULSI interconnect systems demand extremely high data rates (up to
100 Gbps/pin or 20-Tbps aggregate) as well as bidirectional multiI/O concurrent service, re …

Systems with multiple design domains require codesign of application domains. Dedicated
hardware processors implement the application domains and software integrates them. The …

On-chip interconnects are the performance bottleneck in modern system-on-chips. Code-
division multiple access (CDMA) has been proposed to implement on-chip crossbars due to …

A novel approach for mitigation of self-interference in highly-integrated wireless transceivers
is presented. Several examples of possible applications of this approach in a wireless …

On-chip interconnect is a major building block and a main performance bottleneck in
modern complex System-on-Chips (SoCs). The bus topology and its derivatives are the most …

Intra-chip communication is a major bottleneck in modern multiprocessor system-on-chip
(MPSoC) designs. The bus topology is the most common on-chip interconnect technology …

As technology scales toward deep submicron, the integration of complete system-on-chip
(SoC) designs consisting of large number of Intellectual Property (IP) blocks (cores) on the …

The need for an efficient interconnect architecture has been caused by continued increase
of the required communication bandwidth and concurrency of small-scale digital systems …

Accurate timing analysis is key to efficient embedded system synthesis and integration.
While industrial control software systems are developed using graphical models, such as …