Given the significance of placement in IC physical design, extensive research studies
performed over the last 50 years addressed numerous aspects of global and detailed …

Statistical timing analysis is an area of growing importance in nanometer te-nologies ‚as the
uncertainties associated with process and environmental var-tions increase ‚and this …

the present invention relates, in general, to a device-independent, frequency-driven layout
system and method for field programmable gate arrays (" FPGA"). More particularly, the …

We give a generalization, called the limit-bumping algorithm (LBA). of a procedure of
Youssef et. al.[I] that iran&onns initial connection delays into upper lim-its on delay suitable …

This chapter reviews two basic sets of netweighting algorithms: static netweighting and
dynamic netweighting. It explores two global placement approaches: partitioning and force …

Placement is one of the most important steps in the RTL-to-GDSII synthesis process, as it
directly defines the interconnects, which have become the bottleneck in circuit and system …

Modern Placement Techniques explains physical design and VLSI/CAD placement to the
professional engineer and engineering student. Along with explaining the problems that are …

This paper presents a new timing driven force directed placement algorithm that meets
physical net length constraints as well as constraints on specific pin sets. It is the first force …

This paper presents a new performance and routability driven router for symmetrical array
based Field Programmable Gate Arrays (FPGAs). The objectives of our proposed routing …

Generating delay targets for creating a multilevel hierarchical circuit design by providing a
hierarchical design description and delay constraints of the circuit design; generating a net …