[HTML][HTML] Towards Efficient Memory Architectures: Low-Power Noise-Immune RRAM

NM Edward, SM Hamed, WR Anis, N Elaraby - Energies, 2024 - mdpi.com
The performance of Static Nanomaterials Random-Access Memories (SRAMs) is often
degraded in the sub-threshold region as it is susceptible to increased access energy and …

Memristor-Based Power Efficient 4T3M SRAM Cell

NM Edward, SM Hamed, N Elaraby… - 2024 14th International …, 2024 - ieeexplore.ieee.org
Cells for Random Access Memory (RAM) are extensively utilized in many modern electronic
devices. One of the difficult aspects of building Static Random Access Memory (SRAM) cells …

Analysis of static power reduction strategies in deep submicron CMOS device technology for digital circuits

G Munirathnam, YMM Babu - 2021 6th International …, 2021 - ieeexplore.ieee.org
Low power VLSI circuit design faces the challenging issues of static power dissipation as
transistor count doubles for every couple of years. static power dissipation also known as …

Optimizing Power Efficiency in SRAM Cells through Memristor-Based Architectures

NM Edwards, SM Hamed, N Elaraby… - … on Machine Intelligence …, 2024 - ieeexplore.ieee.org
Random Access Memory (RAM) cells find extensive applications in diverse digital electronic
systems. In the realm of Static Random Access Memory (SRAM) cells, minimizing power …

Optimized Speed and Power Consumption in a 14T SRAM Bit Cell by Use of Shorted-Gate FinFET

M Pandey, S Bansal, OA Shah - 2023 3rd International …, 2023 - ieeexplore.ieee.org
In the current state of the technical environment, power optimization, delay reduction, and
leakage minimization are of the utmost importance. This is especially true as the industry …

Low power and noise‐immune 9 T compute SRAM cell design based on differential power generator and Schmitt‐trigger logics with14 nm FinFET technology

P Praveen, RK Singh - International Journal of Circuit Theory and … - Wiley Online Library
The excessive power usage in modern digital equipment is triggered by memory arrays,
mainly including Static Random‐Access Memory (SRAM) chips. Many scientists are working …

Design and Simulation of 32 X 8 Kb Random Access Memory Composed of Reciprocal Magnetic Flux Quanta

S Narendran - … 3rd International Conference on Electronics and …, 2022 - ieeexplore.ieee.org
By 2020, CMOS (complementary metal-oxide semiconductor) technology will be obsolete,
and Post Moore law technology will be vying for low-power, high-speed operation. With both …

A Comparative Study of CMOS and Finfet Sram Cells: Leakage Minimization and Energy Optimization

M Ruj, RVS Reddy - … Conference on Smart Power Control and …, 2024 - ieeexplore.ieee.org
This work presents a comparative analysis of the performance characteristics exhibited by
two established SRAM cell topologies, namely the conventional 6 and the 7 transistor …

Cache Memory Design for Single Bit Architecture for Core ITM Processors

R Agrawal, N Faujdar, MZ Khan - Security and Privacy-Preserving …, 2022 - taylorfrancis.com
This chapter describes the implementation and analysis of cache memory design for single
bit architecture comprised of six transistors static random access memory cell, a circuit of …

47. 14T 14T SRAM Bit Cell with Speed and Power Optimized Using CNTFET

VK Sharma, A Kumar - Intelligent Circuits and Systems for SDG 3 …, 2024 - books.google.com
This article offers a revolutionary design for a 14T SRAM bit cell that makes use of carbon
nanotube field-effect transistors (CNTFETs) in order to strike a compromise between speed …