We analyze the performance of various heuristic algorithms for minimizing realizations of
multiple-valued functions by the newly developed CCD 191 and CMOS [W] programmable …

Novel quaternary logic circuits, designed in 2-mu m CMOS technology, are presented.
These include threshold detector circuits with an improved output voltage swing and a …

ABSTRACT HAMLET is a CAD tool that translates a user specification of a multiple-valued
expression into a layout of a multiple-valued programmable logic array (MVLPLA) which …

A programmable logic array (PLA) structure for implementation of multivalued combinational
and sequential systems is proposed. The PLA is integrable by using a conventional CMOS …

We compare the performance of three heuristic algorithms 3, 6, 13 for the minimization of
sum-of-products expressions realized by the newly developed multiple-valued …

The benefits and current state of the art of charge-coupled-device logic are examined. The
fundamentals of CCD logic operations and basic CCD configurations are presented …

Upper and lower bounds are shown for the average number of product terms required in the
minimal realization, as a function of the number of nonzero output values. The variance, in …

Algorithms for synthesis of four-valued one-and two-variable functions for CCD (charge
coupled device) implementation are proposed. One-variable synthesis is based on the …

We propose a solution to the minimization problem of multiple-valued pro-grammable logic
arrays (PLA) that uses simulated annealing. The algorithm accepts a sum-of-products …

Several approaches have been developed for the synthesis of one-variable 4-valued
functions using CCDs. In all these approaches an attempt has been made to reduce the cost …