Energy-efficient networks-on-chip architectures: Design and run-time optimization
Abstract Networks-on-Chip (NoC) architectures have become the mainstream
communication backbone of high-end processors and systems-on-chip (SoCs) after their …
communication backbone of high-end processors and systems-on-chip (SoCs) after their …
Dypo: Dynamic pareto-optimal configuration selection for heterogeneous mpsocs
Modern multiprocessor systems-on-chip (MpSoCs) offer tremendous power and
performance optimization opportunities by tuning thousands of potential voltage, frequency …
performance optimization opportunities by tuning thousands of potential voltage, frequency …
A systematic analysis of power saving techniques for wireless network-on-chip architectures
F Yazdanpanah, R Afsharmazayejani - Journal of Systems Architecture, 2022 - Elsevier
Wireless network-on-chip (WNoC, aka WiNoC) architectures, as an emerging and viable
alternative approach, overcome the communication constraints and drawbacks of network …
alternative approach, overcome the communication constraints and drawbacks of network …
Imitation learning for dynamic VFI control in large-scale manycore systems
Manycore chips are widely employed in high-performance computing and large-scale data
analysis. However, the design of high-performance manycore chips is dominated by power …
analysis. However, the design of high-performance manycore chips is dominated by power …
Machine learning for design space exploration and optimization of manycore systems
In the emerging data-driven science paradigm, computing systems ranging from IoT and
mobile to manycores and datacenters play distinct roles. These systems need to be …
mobile to manycores and datacenters play distinct roles. These systems need to be …
Performance and thermal tradeoffs for energy-efficient monolithic 3D network-on-chip
Three-dimensional (3D) integration enables the design of high-performance and energy-
efficient network on chip (NoC) architectures as communication backbones for manycore …
efficient network on chip (NoC) architectures as communication backbones for manycore …
Engineer the channel and adapt to it: Enabling wireless intra-chip communication
Ubiquitous multicore processors nowadays rely on an integrated packet-switched network
for cores to exchange and share data. The performance of these intra-chip networks is a key …
for cores to exchange and share data. The performance of these intra-chip networks is a key …
Machine learning and manycore systems design: A serendipitous symbiosis
Tight collaboration between manycore system designers and machine-learning experts is
necessary to create a data-driven manycore design framework that integrates both learning …
necessary to create a data-driven manycore design framework that integrates both learning …
A dynamic programming framework for DVFS-based energy-efficiency in multicore systems
Per-core Dynamic Voltage and Frequency (V/F) Scaling (DVFS) is a well-known
methodology for achieving energy efficiency in multicore systems. Heuristic DVFS …
methodology for achieving energy efficiency in multicore systems. Heuristic DVFS …
Impact of electrostatic coupling on monolithic 3D-enabled network on chip
Monolithic-3D-integration (M3D) improves the performance and energy efficiency of 3D ICs
over conventional through-silicon-vias-based counterparts. The smaller dimensions of …
over conventional through-silicon-vias-based counterparts. The smaller dimensions of …