A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance
A review on CMOS delay lines with a focus on the most frequently used techniques for high-
resolution delay step is presented. The primary types, specifications, delay circuits, and …
resolution delay step is presented. The primary types, specifications, delay circuits, and …
A digitally controlled PLL for SoC applications
T Olsson, P Nilsson - IEEE journal of solid-state circuits, 2004 - ieeexplore.ieee.org
A fully integrated digitally controlled phase-locked loop (PLL) used as a clock multiplying
circuit is designed and fabricated. The PLL has no off-chip components and it is made from …
circuit is designed and fabricated. The PLL has no off-chip components and it is made from …
All-digital phase locked loop (ADPLL) topologies for RFID system application: A review
An all-digital phase locked loop (ADPLL)-based local oscillator (LO) of RF transceiver
application such as radio-frequency identification (RFID) system has gained popularity by …
application such as radio-frequency identification (RFID) system has gained popularity by …
A portable digitally controlled oscillator using novel varactors
This work presents a portable digitally controlled oscillator (DCO) by using two-input NOR
gates as a digitally controlled varactor (DCV) in fine-tuning delay cell design. This novel …
gates as a digitally controlled varactor (DCV) in fine-tuning delay cell design. This novel …
An ultra-low-power and portable digitally controlled oscillator for SoC applications
In this paper, a novel ultra-low-power digitally controlled oscillator (DCO) with cell-based
design for system-on-chip (SoC) applications is presented. Based on the proposed …
design for system-on-chip (SoC) applications is presented. Based on the proposed …
A new DLL-based approach for all-digital multiphase clock generation
A new DLL-based approach for all-digital multiphase clock generation is presented. By
using the time-to-digital converter (TDC) with fixed-step search scheme, the proposed all …
using the time-to-digital converter (TDC) with fixed-step search scheme, the proposed all …
A 0.52/1 V fast lock-in ADPLL for supporting dynamic voltage and frequency scaling
CC Chung, WS Su, CK Lo - IEEE Transactions on Very Large …, 2015 - ieeexplore.ieee.org
In energy-efficient processing platforms, such as wearable sensors and implantable medical
devices, dynamic voltage and frequency scaling allows optimizing the energy efficiency …
devices, dynamic voltage and frequency scaling allows optimizing the energy efficiency …
Glitch-free NAND-based digitally controlled delay-lines
D De Caro - IEEE Transactions on Very Large Scale Integration …, 2012 - ieeexplore.ieee.org
The recently proposed NAND-based digitally controlled delay-lines (DCDL) present a
glitching problem which may limit their employ in many applications. This paper presents a …
glitching problem which may limit their employ in many applications. This paper presents a …
Parameterized all-digital PLL architecture and its compiler to support easy process migration
CW Tzeng, SY Huang, PY Chao - IEEE Transactions on Very …, 2013 - ieeexplore.ieee.org
In this paper, we propose a parameterized digitally controlled oscillator that can produce
oscillating-clock signal with the tunable frequency covering an entire designated range …
oscillating-clock signal with the tunable frequency covering an entire designated range …
A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications
This work presents a clock generator with cascaded dynamic frequency counting (DFC)
loops for wide multiplication range applications. The DFC loop, which uses variable time …
loops for wide multiplication range applications. The DFC loop, which uses variable time …