A flexible, scalable server is described. The server includes plural server nodes each server
node including processor cores and switching circuitry configured to couple the processor to …

(57) ABSTRACT A processor includes a plurality of processor tiles, each tile including a
processor core, and an interconnection network interconnects the processor cores and …

7. B-1 (P1) sends message to Bo (not mapped) Cache miss handled by owner P3 containing
A1 is chosen for pre-empting Ownero asks owner to undo (A1-) P3) map (A1-) P3) entry in …

A plurality of processor tiles are provided, each processor tile including a processor core. An
interconnection network interconnects the processor cores and enables transfer of data …

(57) ABSTRACT A processor has multiple cores with each core having an associated
function to Support processor operations. The functions performed by the cores are …

(57) ABSTRACT A system comprises a plurality of computation units inter connected by an
interconnection network. A method for con figuring the system comprises forming Subsets of …

A method for performing memory disambiguation in an out-of-order microprocessor pipeline
is disclosed. The method comprises storing a tag with a load operation, wherein the tag is an …

2. Description of the Related Art Modern processors have evolved to multi-core architec
tures which utilize two or more on-chip processing cores (cores) per physical chip or …

Abstract Systems, apparatuses, and methods for a hardware and software system to
automatically decompose a program into multiple parallel threads are described. In some …

An information handling system may include a field-programmable gate array (FPGA), and a
hypervisor to manage virtual machines. The hypervisor may host a first FPGA service …