A 0.25 µm SCVL based 4T DRAM design for minimizing leakage current using CMOS technology
S Kulkarni, N Rai - … on Green Computing and Internet of Things …, 2015 - ieeexplore.ieee.org
With the improved technological development of large ICs, system designers characterized
the circuit by reliability, low power dissipation, power consumption, chip density and leakage …
the circuit by reliability, low power dissipation, power consumption, chip density and leakage …
A job completion time estimation method for work center scheduling
TA Owens, PB Luh - … 1991 IEEE International Conference on Robotics …, 1991 - computer.org
With the improved technological development of large ICs, system designers characterized
the circuit by reliability, low power dissipation, power consumption, chip density and leakage …
the circuit by reliability, low power dissipation, power consumption, chip density and leakage …