Machine learning for electronic design automation: A survey

G Huang, J Hu, Y He, J Liu, M Ma, Z Shen… - ACM Transactions on …, 2021 - dl.acm.org
With the down-scaling of CMOS technology, the design complexity of very large-scale
integrated is increasing. Although the application of machine learning (ML) techniques in …

Hardware trust and assurance through reverse engineering: A tutorial and outlook from image analysis and machine learning perspectives

UJ Botero, R Wilson, H Lu, MT Rahman… - ACM Journal on …, 2021 - dl.acm.org
In the context of hardware trust and assurance, reverse engineering has been often
considered as an illegal action. Generally speaking, reverse engineering aims to retrieve …

A customized graph neural network model for guiding analog IC placement

Y Li, Y Lin, M Madhusudan, A Sharma, W Xu… - Proceedings of the 39th …, 2020 - dl.acm.org
Analog IC placement is typically a manual process that requires strong experience and trial-
and-error iterations as it produces a large impact to circuit performance in a complicated …

GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists

L Alrahis, A Sengupta, J Knechtel… - … on Computer-Aided …, 2021 - ieeexplore.ieee.org
This work introduces a generic, machine learning (ML)-based platform for functional reverse
engineering (RE) of circuits. Our proposed platform GNN-RE leverages the notion of graph …

Applications of artificial intelligence on the modeling and optimization for analog and mixed-signal circuits: A review

M Fayazi, Z Colter, E Afshari… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
Recently, there have been many studies attempting to take advantage of advancements in
Artificial Intelligence (AI) in Analog and Mixed-Signal (AMS) circuit design. Automated circuit …

ALIGN: A system for automating analog layout

T Dhar, K Kunal, Y Li, M Madhusudan… - IEEE Design & …, 2020 - ieeexplore.ieee.org
ALIGN: A System for Automating Analog Layout Page 1 8 2168-2356/20©2020 IEEE
Copublished by the IEEE CEDA, IEEE CASS, IEEE SSCS, and TTTC IEEE Design&Test …

A comprehensive survey on electronic design automation and graph neural networks: Theory and applications

D Sánchez, L Servadei, GN Kiprit, R Wille… - ACM Transactions on …, 2023 - dl.acm.org
Driven by Moore's law, the chip design complexity is steadily increasing. Electronic Design
Automation (EDA) has been able to cope with the challenging very large-scale integration …

A general approach for identifying hierarchical symmetry constraints for analog circuit layout

K Kunal, J Poojary, T Dhar, M Madhusudan… - Proceedings of the 39th …, 2020 - dl.acm.org
Analog layout synthesis requires some elements in the circuit netlist to be matched and
placed symmetrically. However, the set of symmetries is very circuit-specific and a versatile …

Graph neural networks: A powerful and versatile tool for advancing design, reliability, and security of ICs

L Alrahis, J Knechtel, O Sinanoglu - Proceedings of the 28th Asia and …, 2023 - dl.acm.org
Graph neural networks (GNNs) have pushed the state-of-the-art (SOTA) for performance in
learning and predicting on large-scale data present in social networks, biology, etc. Since …

Deep H-GCN: Fast analog IC aging-induced degradation estimation

T Chen, Q Sun, C Zhan, C Liu, H Yu… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
With continued scaling, the transistor aging induced by hot carrier injection (HCI) and bias
temperature instability (BTI) causes an increasing failure of nanometer-scale integrated …