An effective way to reduce supply voltage and resulting power consumption without losing
the circuit performance of CMOS is to use CMOS structures using high carrier …

A test-chip in a low-power 45 nm technology, featuring uniaxial strained-Si, has been built to
study variability in CMOS circuits. Systematic layout-induced variation, die-to-die (D2D) …

In this letter, we propose a lateral asymmetric strain profile in a silicon nanowire or ultrathin
silicon film as a key technology booster for the performance of all-silicon tunnel FETs. We …

A combination of the materials science, manufacturing processes, and pioneering research
and developments of SiGe and strained-Si have offered an unprecedented high level of …

We present experimental results on on-current and transconductance gain and mobility
enhancement in Si nanowire FETs (NW-FETs) fabricated on silicon-on-insulator (SOI) and …

This paper presents an extensive simulation study of a MOSFET with reverse embedded-
SiGe (Rev. e-SiGe), a new strained-silicon concept that utilizes elastic relaxation of a buried …

In this letter, the SiGe-channel PMOS transistors integrated with a highly compressive
contact-etching stop-layer (CESL) interlayer-dielectric-SiN x stressing layer have been …

Impact of strained silicon effects in double-gated FinFET structures on static random access
memory (SRAM) cell functionality is presented. Three FinFET silicon-on-insulator (SOI) …

In previous publications we have proposed a hierarchical variability model and verified it
with 90nm test data. This model is now validated with a new set of 45nm test chips. A mixed …

In this letter, we investigate the impact of a hybridized strain technology on the performance
of FinFET-based multigate field-effect transistors (MUGFETs). The technology combines the …