A ring-oscillator-based degradation monitor concept with tamper detection capability

J Diaz-Fortuny, P Saraza-Canflanca… - 2022 IEEE …, 2022 - ieeexplore.ieee.org
Refurbished chips (ie, chips re-used legally in circular economy) and counterfeited chips (ie,
used chips fraudulently sold as new) are a growing concern for the industry because of their …

Improving the Tamper-Aware Odometer Concept by Enhancing Dynamic Stress Operation

J Diaz-Fortuny, D Sangani… - 2023 IEEE …, 2023 - ieeexplore.ieee.org
On-chip degradation monitors have recently gained significant relevance because they can
provide real-time estimations of IC reliability by exploiting the fundamental physics of BTI …

Flexible setup for the measurement of CMOS time-dependent variability with array-based integrated circuits

J Diaz-Fortuny, P Saraza-Canflanca… - IEEE Transactions …, 2019 - ieeexplore.ieee.org
This paper presents an innovative and automated measurement setup for the
characterization of variability effects in CMOS transistors using array-based integrated …

Towards complete recovery of circuit degradation by annealing with on-chip heaters

J Diaz-Fortuny, P Saraza-Canflanca… - IEEE Electron …, 2022 - ieeexplore.ieee.org
This work reports an on-chip heater structure fabricated in the Front End of Line (FEOL) on a
versatile ring-oscillator (RO) array utilized to conduct statistical characterization of on-chip …

Statistical characterization of time-dependent variability defects using the maximum current fluctuation

P Saraza-Canflanca, J Martín-Martínez… - … on Electron Devices, 2021 - ieeexplore.ieee.org
This article presents a new methodology to extract, at a given operation condition, the
statistical distribution of the number of active defects that contribute to the observed device …

An automated setup for the characterization of time-based degradation effects including the process variability in 40-nm CMOS transistors

X Xhafa, AD Güngördü, D Erol, Y Yavuz… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
This article reports a test chip design in commercial 40-nm process technology to
characterize the level of time-based degradation in metal-oxide-semiconductor field-effect …

A detailed study of the gate/drain voltage dependence of RTN in bulk pMOS transistors

P Saraza-Canflanca, J Martín-Martínez… - Microelectronic …, 2019 - Elsevier
Abstract Random Telegraph Noise (RTN) has attracted increasing interest in the last years.
This phenomenon introduces variability in the electrical properties of transistors, in particular …

A robust and automated methodology for the analysis of Time-Dependent Variability at transistor level

P Saraza-Canflanca, J Diaz-Fortuny, R Castro-López… - Integration, 2020 - Elsevier
In the past few years, Time-Dependent Variability has become a subject of growing concern
in CMOS technologies. In particular, phenomena such as Bias Temperature Instability, Hot …

A Unified Framework to Explain Random Telegraph Noise Complexity in MOSFETs and RRAMs

S Vecchi, P Pavan, FM Puglisi - 2023 IEEE International …, 2023 - ieeexplore.ieee.org
As well known, the implementation of high-κ dielectrics (eg, HfO_2) in nanoscale devices is
unavoidable to cope with the device scaling required by the market. Nevertheless, due to the …

A 1.8-V GPIO With Design-Technology-Reliability Co-Optimization in Sub-3-nm GAA-NS Technology

WC Chen, SH Chen, MC Huang… - IEEE Journal of Solid …, 2024 - ieeexplore.ieee.org
In this work, the challenge of the I/O development roadmap is discussed. Utilizing design
and technology co-optimization (DTCO), a cost-effective circuit solution of a 1.8-V general …