Low‐Temperature Polysilicon Oxide Thin‐Film Transistors with Coplanar Structure Using Six Photomask Steps Demonstrating High Inverter Gain of 264 V V−1
DY Jeong, Y Chang, WG Yoon, Y Do… - Advanced Engineering …, 2020 - Wiley Online Library
The low‐temperature polysilicon oxide (LTPO) complementary metal‐oxide‐semiconductor
(CMOS) thin‐film transistors (TFTs) is fabricated by p‐type low‐temperature polysilicon …
(CMOS) thin‐film transistors (TFTs) is fabricated by p‐type low‐temperature polysilicon …
The characteristics of solid phase crystallized (SPC) polycrystalline silicon thin film transistors employing amorphous silicon process
WK Lee, SM Han, J Choi, MK Han - Journal of non-crystalline solids, 2008 - Elsevier
We investigated the electrical properties of polycrystalline silicon (poly-Si) thin film
transistors (TFTs) employing field-enhanced solid phase crystallization (FESPC). An n+ …
transistors (TFTs) employing field-enhanced solid phase crystallization (FESPC). An n+ …
Suppression of leakage current in solid-phase crystallization silicon thin-film transistors employing off-state-bias annealing
SG Park, WK Lee, SJ Kim, MK Han - Japanese Journal of …, 2009 - iopscience.iop.org
We have fabricated p-channel metal oxide semiconductor (PMOS) solid-phase
crystallization silicon (SPC-Si) thin-film transistors (TFTs) employing an alternating magnetic …
crystallization silicon (SPC-Si) thin-film transistors (TFTs) employing an alternating magnetic …
The characteristics of new n-type polycrystalline silicon thin-film transistors employing alternating magnetic-field-enhanced rapid thermal annealing
WK Lee, JH Park, J Choi, MK Han - IEEE electron device letters, 2008 - ieeexplore.ieee.org
We fabricated a new top-gate n-type depletion-mode polycrystalline silicon (poly-Si) thin-film
transistor (TFT) employing alternating magnetic-field-enhanced rapid thermal annealing. An …
transistor (TFT) employing alternating magnetic-field-enhanced rapid thermal annealing. An …
Effect of a channel length and drain bias on the threshold voltage of field enhanced solid phase crystallization polycrystalline thin film transistor on the glass substrate
WK Lee, SM Han, SG Park, YJ Chang… - MRS Online …, 2007 - cambridge.org
We have fabricated a new magnetic field enhanced solid phase crystallization (FESPC)
polycrystalline silicon (poly-Si) thin film transistors (TFTs), which shows the excellent …
polycrystalline silicon (poly-Si) thin film transistors (TFTs), which shows the excellent …
Asymmetric source/drain offset structure for reduced leakage current in polycrystalline‐silicon thin‐film transistors
WK Lee, HS Park, BS Jeong, J Choi… - Journal of the …, 2009 - Wiley Online Library
An asymmetric source/drain offset structured (AOS) polycrystalline‐silicon (poly‐Si) thin‐film
transistor (TFT) has ben developed by employing alternating magnetic‐field‐enhanced …
transistor (TFT) has ben developed by employing alternating magnetic‐field‐enhanced …
Thin film transistor panel, electric device including the same, and manufacturing method thereof
DY Jeong, CY Hwang, DG Eo - US Patent 11,616,086, 2023 - Google Patents
US11616086B2 - Thin film transistor panel, electric device including the same, and manufacturing
method thereof - Google Patents US11616086B2 - Thin film transistor panel, electric device …
method thereof - Google Patents US11616086B2 - Thin film transistor panel, electric device …
The Characteristics of Hot-Carrier Stressed Bottom-Gate Polycrystalline Silicon Thin-Film Transistors Employing Alternating Magnetic-Field-Enhanced Rapid Thermal …
WK Lee, HS Shin, K Cho, J Choi, CW Kim… - ECS …, 2008 - iopscience.iop.org
We have evaluated the reliability of the bottom-gate (BG) polycrystalline silicon (poly-Si) thin-
film transistors (TFTs) by employing alternating magnetic-field-enhanced rapid thermal …
film transistors (TFTs) by employing alternating magnetic-field-enhanced rapid thermal …
[PDF][PDF] 교류자계유도결정화된다결정박막트랜지스터의비대칭오프셋구조를통한누설전류감소효과
강동원， 이원규， 한상면， 최준후， 김치우… - 대한전기학회학술대회 …, 2008 - koreascience.kr
N 형 공핍 모드의 탑 게이트 다결정실리콘 박막 트랜지스터에 비대칭 오프셋 구조를
적용하였다. 이로써 드레인 부근의 전계를감소시켜, on 전류의 큰 손실 없이 누설 전류를 86 …
적용하였다. 이로써 드레인 부근의 전계를감소시켜, on 전류의 큰 손실 없이 누설 전류를 86 …
The Effect of Electrical Stress on the New Top Gate N-type Depletion Mode Polycrystalline Thin Film Transistors Fabricated by Alternating Magnetic Field Enhanced …
WK Lee, SM Han, SG Park, SH Choi, J Choi… - MRS Online …, 2008 - cambridge.org
We have fabricated the new top gate depletion mode n-type alternating magnetic field
enhanced rapid thermal annealing (AMFERTA) polycrystalline silicon (poly-Si) thin film …
enhanced rapid thermal annealing (AMFERTA) polycrystalline silicon (poly-Si) thin film …