Methods of generating an integrated circuit layout include forming a standard cell by
providing a first active area adjacent to a first cell boundary line. The first active area is …

ABSTRACT A semiconductor device includes a plurality of active regions including channel
regions extending in a first direc tion on a semiconductor substrate and source/drain regions …

(57) ABSTRACT A system and method for efficiently creating layout for a standard cell are
described. A standard cell to be used for an integrated circuit uses a full trench silicide strap …

An integrated circuit includes a first cell arranged in a first row extending in a first horizontal
direction, a second cell arranged in a second row adjacent to the first row, and a third cell …

HOIL 23/52(2006. 01) HOIL 23/528(2006. 01) HOIL 23/522(2006. 01) HOIL 23/58(2006. 01)
HOIL 27/02(2006. 01) G06F 17/50(2006. 01) HOIL 29/78(2006. 01) HOIL 21/02(2006. 01) …

A semiconductor device includes a semiconductor substrate and a plurality of metal layers
above the semiconductor substrate. A first of the metal layers includes a plurality of first …

(57) ABSTRACT A semiconductor device having a plurality of first wirings (X-direction) which
include a first power supply line and a second power supply line, a plurality of third wirings …

In an exemplary structure, a first conductor connects a power source to integrated circuit
devices. The first conductor includes a first axis defining a first side and a second side. A …

Standard cell circuits employing high aspect ratio voltage rails for reduced resistance are
disclosed. In one aspect, a standard cell circuit is provided that employs a first high aspect …

(57) ABSTRACT A system and method for creating chip layout are described. In various
embodiments, a standard cell uses unidirectional tracks for power connections and signal …