3-D technology provides many benefits including high density, high bandwidth, low-power,
and small form-factor. Through Silicon Via (TSV), which provides communication links for …

Physical limit of transistor miniaturization has driven chip design into the third dimension. 3D
integration technology emerges as a viable option to improve chip performance and …

The decoupling of modern printed circuit boards introduces a very complex task. Powerful
stochastic optimizers are usually used to determine values and positions of decoupling …

Three primary techniques for manufacturing through silicon vias (TSVs), via-first, via-middle,
and via-last, have been analyzed and compared to distribute power in a 3-D processor …

3-D integration has the potential to increase performance and decrease energy
consumption. However, there are many unsolved issues in the design of these systems. In …

Increasing test coverage of power integrity in manufacturing test of 3D-ICs is necessary to
achieve zero DPPM (Defect Parts Per Million) in the market. Although only functional tests …

Ioannis Savidis was born in Rochester, New York in December 1982. He received the BSE
degree in electrical and computer engineering and biomedical engineering from Duke …

In traditional decoupling capacitor topologies, power gating can significantly degrade the
system-wide power integrity of a 3-D integrated circuit since the decoupling capacitance …

Power integrity is generally considered to be one of the major bottlenecks hindering the
prevalence of three-dimensional integrated circuits (3D ICs). The higher integration density …

In this paper, we propose a method to minimize resources of power distribution networks
(PDNs) in a three-dimensional integrated circuit (3D IC) under the given design constraints …