[图书][B] Memory systems: cache, DRAM, disk
B Jacob, D Wang, S Ng - 2010 - books.google.com
Is your memory hierarchy stopping your microprocessor from performing at the high level it
should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem …
should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem …
SOI for digital CMOS VLSI: Design considerations and advances
CT Chuang, PF Lu, CJ Anderson - Proceedings of the IEEE, 1998 - ieeexplore.ieee.org
This paper reviews the recent advances of silicon-on-insulator (SOI) technology for
complementary metal-oxide-semiconductor (CMOS) very-large-scale-integration memory …
complementary metal-oxide-semiconductor (CMOS) very-large-scale-integration memory …
A 160-mhz, 32-b, 0.5-w CMOS RISC microprocessor
J Montanaro, RT Witek, K Anne… - IEEE Journal of Solid …, 1996 - ieeexplore.ieee.org
This paper describes a 160 MHz 500 mW 32 b StrongARM (R) microprocessor designed for
low-power, low-cost applications. The chip implements the ARM (R) V4 instruction set and is …
low-power, low-cost applications. The chip implements the ARM (R) V4 instruction set and is …
The density advantage of configurable computing
A DeHon - Computer, 2000 - ieeexplore.ieee.org
More and more, field-programmable gate arrays (FPGAs) are accelerating computing
applications. The absolute performance achieved by these configurable machines has been …
applications. The absolute performance achieved by these configurable machines has been …
High-performance microprocessor design
PE Gronowski, WJ Bowhill, RP Preston… - IEEE Journal of Solid …, 1998 - ieeexplore.ieee.org
Three generations of Alpha microprocessors have been designed using a proven custom
design methodology. The performance of these microprocessors was optimized by focusing …
design methodology. The performance of these microprocessors was optimized by focusing …
Noise in deep submicron digital design
KL Shepard, V Narayanan - Proceedings of International …, 1996 - ieeexplore.ieee.org
As technology scales into the deep submicron regime, noise immunity is becoming a metric
of comparable importance to area, timing, and power for the analysis and design of VLSI …
of comparable importance to area, timing, and power for the analysis and design of VLSI …
[图书][B] The VLSI handbook
WK Chen - 1999 - taylorfrancis.com
Over the years, the fundamentals of VLSI technology have evolved to include a wide range
of topics and a broad range of practices. To encompass such a vast amount of knowledge …
of topics and a broad range of practices. To encompass such a vast amount of knowledge …
Skew-tolerant domino circuits
D Harris, MA Horowitz - IEEE Journal of Solid-State Circuits, 1997 - ieeexplore.ieee.org
Domino circuits are widely used in high-performance CMOS microprocessors. However,
textbook domino pipelines suffer significant timing overhead from clock skew, latch delay …
textbook domino pipelines suffer significant timing overhead from clock skew, latch delay …
Impact of scaling on soft-error rates in commercial microprocessors
N Seifert, X Zhu, LW Massengill - IEEE Transactions on Nuclear …, 2002 - ieeexplore.ieee.org
The impact of technology scaling and logic design on the/spl alpha/-particle and neutron-
induced soft-error rate (SER) of Alpha microprocessors (HP Alpha Development Group …
induced soft-error rate (SER) of Alpha microprocessors (HP Alpha Development Group …
SRT division architectures and implementations
DL Harris, SF Oberman… - Proceedings 13th IEEE …, 1997 - ieeexplore.ieee.org
SRT [Sweeney, Robertson and Tocher (1958)] dividers are common in modern floating point
units. Higher division performance is achieved by retiring more quotient bits in each cycle …
units. Higher division performance is achieved by retiring more quotient bits in each cycle …