[图书][B] Introduction to Asynchronous Circuit Design.

J Sparsø - 2020 - orbit.dtu.dk
This book is an introduction to the design of asynchronous circuits. It is an updated and
significantly extended version of an eight-chapter tutorial that first appeared as Part I in the …

An open-source eda flow for asynchronous logic

S Ataei, W Hua, Y Yang, R Manohar, YS Lu… - IEEE Design & …, 2021 - ieeexplore.ieee.org
An Open-Source EDA Flow for Asynchronous Logic Page 1 27 2168-2356/21©2021 IEEE
Copublished by the IEEE CEDA, IEEE CASS, IEEE SSCS, and TTTC March/April 2021 Editor’s …

A robust and self-adaptive clocking technique for SFQ circuits

RN Tadros, PA Beerel - IEEE Transactions on Applied …, 2018 - ieeexplore.ieee.org
Living on the verge of the IoT era, the entire world is excited about the potential of mining the
monumental amounts of data that would become available in the near future. However, this …

Cyclone: A static timing and power engine for asynchronous circuits

W Hua, YS Lu, K Pingali… - 2020 26th IEEE …, 2020 - ieeexplore.ieee.org
Asynchronous circuits have potential advantages of higher speed and lower power
consumption compared to their synchronous counterparts, but their poor CAD support is a …

Opportunistic mutual exclusion

K Srinivasan, Y Moses… - 2023 28th IEEE …, 2023 - ieeexplore.ieee.org
Mutual exclusion is an important problem in the context of shared resource usage, where
only one process can be using the shared resource at any given time. A mutual exclusion …

[PDF][PDF] An open-source design flow for asynchronous circuits

R Manohar - Proc. Government Microcircuit Appl. Crit. Technol. Conf …, 2019 - csl.yale.edu
There have been a number of small-scale and large-scale technology demonstrations of
asynchronous circuits, showing that they have benefits in performance and powerefficiency …

Causal Path Identification for Timed and Sequential Circuits

MJ Wibbels, KS Stevens - IEEE Transactions on Computer …, 2021 - ieeexplore.ieee.org
Self-timed and pulse mode circuit modules are often implemented using combinational logic
with feedback, or require timing constraints for the circuit to function correctly. Identifying …

Static timing analysis induced simulation errors for asynchronous circuits

S Simoglou, C Sotiriou, N Blias - 2021 IEEE International …, 2021 - ieeexplore.ieee.org
In this paper, we demonstrate that conventional Static Timing Anaysis (STA) based,
functional, gate-level simulation of asynchronous circuits with cycles is only as accurate as …

Graph-based STA for asynchronous controllers

S Simoglou, N Xiromeritis, C Sotiriou, N Sketopoulos - Integration, 2020 - Elsevier
We present a Graph-based Asynchronous Static Timing Analysis (ASTA) methodology for
Asynchronous Control Circuits, which pessimistically computes Critical Cycle (s), instead of …

Timing Driven Verification and Optimization of Relative Timed Systems

MJ Wibbels - 2023 - search.proquest.com
Relative timed (RT) circuits have shown area, power, and performance benefits over
synchronous circuits in a number of applications. A primary impediment in the widespread …