Evaluating architectural, redundancy, and implementation strategies for radiation hardening of FinFET integrated circuits

S Pagliarini, L Benites, M Martins… - … on Nuclear Science, 2021 - ieeexplore.ieee.org
In this article, authors explore radiation hardening techniques through the design of a test
chip implemented in 16-nm FinFET technology, along with architectural and redundancy …

Validation of RTL laser fault injection model with respect to layout information

A Papadimitriou, M Tampas, D Hély… - … Security and Trust …, 2015 - ieeexplore.ieee.org
In order for modern security implementations to be trusted, they need to be successfully
evaluated against hardware fault attacks. Lasers are excellent means of introducing either …

MOMENT: A cross-layer method to mitigate multiple event transients in combinational circuits

AM Hajisadeghi, H Bardareh… - 2018 21st Euromicro …, 2018 - ieeexplore.ieee.org
By decreasing transistors feature size in nanoscale technology, the effect of soft error on
combinational circuits has become a challenging problem as the particle strikes may lead to …

Analysis of laser-induced errors: RTL fault models versus layout locality characteristics

A Papadimitriou, D Hély, V Beroulle, P Maistri… - Microprocessors and …, 2016 - Elsevier
Laser attacks are an effective threat against secure integrated circuits, due to their capability
to inject very precise hardware faults. Evaluating the effect of such attacks from RTL …

A Soft-Error Mitigation Approach Using Pulse Quenching Enhancement at Detailed Placement for Combinational Circuits

X He, Y Wang, C Liu, Q Wu, J Luo, Y Guo - ACM Transactions on Design …, 2023 - dl.acm.org
As technology continuously shrinks, radiation-induced soft errors have become a great
threat to the circuit reliability. Among all the causes, the Single-Event Transient (SET) effect …

Detailed placement for pulse quenching enhancement in anti-radiation combinational circuit design

C Liu, X He, B Liang, Y Guo - Integration, 2018 - Elsevier
Pulse width of single event transient can be shrunk by pulse quenching effect in
combinational circuits. And it is found that the pulse quenching effect is closely related to the …

Improved multiple faults-aware placement strategy: Reducing the overheads and error rates in digital circuits

MI Bandan, S Pagliarini, J Mathew… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
State-of-the-art commercial placement tools have as goals to optimize area, timing, and
power. Over the years, several reliability oriented placement strategies have been proposed …

Relative logic cell placement for mitigation of charge sharing-induced transients

BT Kiddie, WH Robinson - Semiconductor Science and …, 2016 - iopscience.iop.org
Abstract Design of modern integrated circuits increasingly requires consideration of
radiation effects, especially in space and other high-risk environments. With fabrication …

CLEAR: a cross-layer soft error rate reduction method based on mitigating DETs in nanoscale combinational logics

AM Hajisadeghi, HR Zarandi - Microprocessors and Microsystems, 2021 - Elsevier
The effects of soft error in combinational logics are challenged by decreasing the feature
size of transistors in nanoscale technologies. Moreover, the single event transients (SETs) …

SeaPlace: Process Variation Aware Placement for Reliable Combinational Circuits against SETs and METs

K Saremi, H Pedram, B Ghavami, M Raji… - arXiv preprint arXiv …, 2021 - arxiv.org
Nowadays nanoscale combinational circuits are facing significant reliability challenges
including soft errors and process variations. This paper presents novel process variation …