Recent advances in semiconductor technology provide us with the resources to explore
alternative methods for fabricating transistors with the goal of further reducing their sizes to …

In this study, conventional CMOS and complementary field-effect transistor (CFET) inverters
based on a vertically stacked-nanosheet (NS) structure were fabricated. The NS below 8-nm …

Present work demonstrates the vertically double stacked nanosheet (NS) p-channel
polycrystalline silicon (poly-Si) junctionless field-effect transistors (JL-FET) with tri-gate …

As the level of integration of IC increases, System on Chip (SoC) design has evolved. This
technology comprises of several intellectual property blocks on a single chip. With …

This report introduces the cryogenic operation and storage performance of 3-D flash
memory. The cell transistor characteristics and the basic functionalities, including read and …

In this paper, we propose the use of silicon carbide (SiC) material in a planar junctionless
FET (JLFET) architecture for high-voltage operations. Using calibrated device simulations …

This paper presents the impacts of an advanced shell doping profile (SDP) on the electrical
characteristics of a junctionless (JL) FET in terms of OFF-current, subthreshold swing (SS) …

In this paper, the n-type and p-type SiGe junctionless bulk FinFET (SiGe JL-FinFET) with a
high Ge mole fraction (xF> 0.8) was studied for characteristics of a single device and the …

This comprehensive study of the horizontally p-type stacked nanosheets inversion mode
thinfilm transistor with gate-all-around (SNS-GAATFT) and multi-gate (SNS-TFT) structures …

In this article, a Heterogeneous Gate-Dielectric Nanosheet Tunnel Field Effect Transistor
(HD-NSH-TFET) with three channels is investigated using the 3-D Visual TCAD simulator …