(57) ABSTRACT A multithreading microprocessor has a plurality of thread contexts (TCs)
each including Sufficient state. Such as general purpose registers and program counter, to …

A multiprocessor computer system includes an exception domain having multiple thread
contexts (TCs) each having a restart address register, and a timer that generates a periodic …

Related US Application Data (60) Division of application No. 1 1/330,915, filed on Jan. 11,
2006, now Pat. No. 7,836,450, which is a continuation-in-part of application No. 1 1/313,272 …

A mechanism for processing in a processor enabled to support and execute multiple
program threads includes a parameter for scheduling a program thread and an instruction …

A multiprocessing system is disclosed. The system includes a multithreading microprocessor
having a plurality of thread contexts (TCs), a translation lookaside buffer (TLB) shared by the …

(57) ABSTRACT A fork instruction for execution on a multithreaded micro processor and
occupying a single instruction issue slot is disclosed. The fork instruction, executing in a …

The present invention addresses the aforementioned prob lems. An object of the present
invention is to provide a system and method capable of performing real-time pro cessing of …

A digital frequency modulator is disclosed. In the digital frequency modulator, a first gain
controller multiplies an input digital signal by a first gain determined according to a required …

Power is conserved by dynamically applying clocks to execution units in a pipeline of a
microprocessor. A clock to an execution unit is applied only when an instruction to the …

Dynamic power management in a processor design is pre sented. A pipeline stage's stall
detection logic detects a stall condition, and sends a signal to idle detection logic to gate off …