Characterizing SRAM and FF soft error rates with measurement and simulation
M Hashimoto, K Kobayashi, J Furuta, SI Abe… - Integration, 2019 - Elsevier
Soft error originating from cosmic ray is a serious concern for reliability demanding
applications, such as autonomous driving, supercomputer, and public transportation system …
applications, such as autonomous driving, supercomputer, and public transportation system …
High robust and cost effective double node upset tolerant latch design for nanoscale CMOS technology
H Li, L Xiao, J Li, C Qi - Microelectronics Reliability, 2019 - Elsevier
In this paper, we propose a novel high reliability and low cost DNU (Double Node Upset)
tolerant latch, HRCE (High Robust and Cost Effective) latch, for nanoscale CMOS …
tolerant latch, HRCE (High Robust and Cost Effective) latch, for nanoscale CMOS …
Wide-range many-core SoC design in scaled CMOS: Challenges and opportunities
The system-on-chip (SoC) designs for future Internet of Things (IoT) systems, spanning client
platforms to cloud datacenters, need to deliver uncompromising and scalable performance …
platforms to cloud datacenters, need to deliver uncompromising and scalable performance …
SEU characterization of commercial and custom-designed SRAMs based on 90 nm technology and below
The R2E project at CERN has tested a few commercial SRAMs and a custom-designed
SRAM, whose data are complementary to various scientific publications. The experimental …
SRAM, whose data are complementary to various scientific publications. The experimental …
A 32 kb macro with 8T soft error robust, SRAM cell in 65-nm CMOS
JS Shah, D Nairn, M Sachdev - IEEE Transactions on Nuclear …, 2015 - ieeexplore.ieee.org
A 32-kb macro containing an eight-transistor soft error robust SRAM cell with differential
read and write capabilities is presented. The 8T cell does not have dedicated access …
read and write capabilities is presented. The 8T cell does not have dedicated access …
Supply voltage dependence of heavy ion induced SEEs on 65 nm CMOS bulk SRAMs
Soft Error Rates (SER) of hardened and unhardened SRAM cells need to be experimentally
characterized to determine their appropriate applications in radiation environments. This …
characterized to determine their appropriate applications in radiation environments. This …
Measurement and mechanism investigation of negative and positive muon-induced upsets in 65-nm bulk SRAMs
W Liao, M Hashimoto, S Manabe… - … on Nuclear Science, 2018 - ieeexplore.ieee.org
Irradiation experiments of positive and negative muon were conducted for 65-nm bulk
CMOS static random-access memory. The experimental results reveal that parasitic bipolar …
CMOS static random-access memory. The experimental results reveal that parasitic bipolar …
SEU characterization of three successive generations of COTS SRAMs at ultralow bias voltage to 14.2-MeV neutrons
This paper presents a single event upset (SEU) sensitivity characterization at ultralow bias
voltage of three generations of commercial off-the-shelf static random access memories …
voltage of three generations of commercial off-the-shelf static random access memories …
Sensitivity characterization of a COTS 90-nm SRAM at ultralow bias voltage
This paper presents the characterization of the sensitivity to 14-MeV neutrons of a
commercial off-the-shelf 90-nm static random access memories manufactured by Cypress …
commercial off-the-shelf 90-nm static random access memories manufactured by Cypress …
Angular dependency of neutron-induced multiple cell upsets in 65-nm 10T subthreshold SRAM
This paper reports neutron-induced MCU (Multiple Cell Upset) measured in 0.4-V 65-nm
10T SRAM at two incident angles of 0° and 60°. The measurement results show that the ratio …
10T SRAM at two incident angles of 0° and 60°. The measurement results show that the ratio …