BIST-based fault diagnosis for PCM with enhanced test scheme and fault-free region finding algorithm
As one of the most promising candidates for nonvolatile memory, phase change memory
(PCM) technology has shown great performance advantages in market applications …
(PCM) technology has shown great performance advantages in market applications …
An In-Array Build-In Self-Test Scheme for Embedded SRAM Array
F Wei, X Cui, S Zhang - … Transactions on Circuits and Systems II …, 2024 - ieeexplore.ieee.org
An in-array Build-In Self-Test (BIST) scheme is proposed for the embedded SRAM array.
The linear feedback shift register (LFSR) is used to implement the pattern generator, and the …
The linear feedback shift register (LFSR) is used to implement the pattern generator, and the …
Optimization of experimental designs for system-level accelerated life test in a memory system degraded by time-dependent dielectric breakdown
Continuous memory technology scaling causes memory cells to be vulnerable to wearout.
To ensure reliable operations of circuits and systems in the presence of wearout, we require …
To ensure reliable operations of circuits and systems in the presence of wearout, we require …
Bridge-defect prediction in SRAM circuits using random forest, XGBoost, and LightGBM learners
J Ghosh, SY Lim, AVY Thean - 2021 International Conference …, 2021 - ieeexplore.ieee.org
The modern fabrication technology node for devices and circuits is causing several failure
analysis challenges of the current state-of-the-art tools to actually find the location of the …
analysis challenges of the current state-of-the-art tools to actually find the location of the …
An ECC-assisted postpackage repair methodology in main memory systems
As dynamic random access memories (DRAMs) operate in the field, hard errors resulting
from wearout occur. Unless corrected or repaired, hard errors halt normal operations …
from wearout occur. Unless corrected or repaired, hard errors halt normal operations …
A Simulation Approach to Analyze Bridge-Defects in a 6T-SRAM Bit Cell
J Ghosh, SY Lim, FM Meftahul… - 2022 6th IEEE …, 2022 - ieeexplore.ieee.org
The modern semiconductor technology node causes several failure analysis challenges of
the current industry-standard tools to locate the physical defects. Here we discuss such …
the current industry-standard tools to locate the physical defects. Here we discuss such …
[PDF][PDF] Dynamic estimation of temporary failure in SoC FPGAs for heterogeneous applications
J Kokila, N Ramasubramanian… - J. Universal Comput. Sci, 2018 - academia.edu
Recent processors are shrinking in size due to the advancement of technology. Reliability is
an important design parameter along with power, cost, and performance. The processors …
an important design parameter along with power, cost, and performance. The processors …
TDDB-emerald: A methodology for estimating memory reliability degradation resulting from time-dependent dielectric breakdown
One of the major wearout mechanisms in modern microprocessors is time-dependent
dielectric breakdown. Beyond the 28 nm technology node, time-dependent dielectric …
dielectric breakdown. Beyond the 28 nm technology node, time-dependent dielectric …
Extraction of wearout model parameters using on-line test of an SRAM
To accurately determine the reliability of SRAMs, we propose a method to estimate the
wearout parameters of FEOL TDDB using on-line data collected during operations. Errors in …
wearout parameters of FEOL TDDB using on-line data collected during operations. Errors in …
Optimal accelerated test framework for time-dependent dielectric breakdown lifetime parameter estimation
A framework is presented to identify an optimal accelerated test region and accelerated test
conditions for the accelerated test of logic circuits for time-dependent dielectric breakdown …
conditions for the accelerated test of logic circuits for time-dependent dielectric breakdown …