Method and apparatus for delayed recursion decoder

R Hegde, A Singer, J Janovetz - US Patent 7,206,363, 2007 - Google Patents
A high-speed maximum likelihood sequence estimation method and device. The method
includes identifying candidate paths through a state trellis based on a group of observed …

A 500-Mb/s soft-output Viterbi decoder

E Yeo, SA Augsburger, WR Davis… - IEEE Journal of Solid …, 2003 - ieeexplore.ieee.org
Two eight-state 7-bit soft-output Viterbi decoders matched to an EPR4 channel and a rate-
8/9 convolutional code are implemented in a 0.18-μm CMOS technology. The throughput of …

Baseband phase-locked loop

HM Bae, NR Shanbhag, AC Singer - US Patent 8,358,729, 2013 - Google Patents
correction signal, wherein the second control Voltage corrects for an offset error present in
the first control voltage, calcu lating a VCO control signal based on a linear combination of …

Tuning system and method using a simulated bit error rate for use in an electronic dispersion compensator

JB Ashbrook, AC Singer, NR Shanbhag… - US Patent …, 2012 - Google Patents
A system and method is disclosed for controlling signal conditioning parameters and a
sampling parameter controlling conversion of a received signal to digital sampled values …

[图书][B] Algorithm/architecture co-design for wireless communications systems

N Zhang - 2001 - search.proquest.com
Wireless connectivity is playing an increasingly significant role in communication systems.
Advanced communication algorithms have been developed to combat multi-path and multi …

Method and apparatus for Viterbi detection of generalized partial response signals using partial matched filter and matched filter metrics

RD Cideciyan, JD Coker, ES Eleftheriou… - US Patent …, 2002 - Google Patents
(56) References Cited varying terms and the shifted constant terms are added directly to
State metric terms. The time varying terms are US PATENT DOCUMENTS expressed as …

Method and apparatus for delayed recursion decoder

R Hegde, A Singer, J Janovetz - US Patent 8,085,883, 2011 - Google Patents
A high-speed maximum likelihood sequence estimation method and device. The method
includes identifying candidate paths through a state trellis based on a group of observed …

通道解碼器之設計與實作

林建青, 李鎮宜, 張錫嘉 - 2005 - ir.lib.nycu.edu.tw
本論文由演算法到架構設計與電路實現探討通道解碼器. 依解碼方式不同可分成三個主要部分
討論, 分別是代數解碼, 機率解碼以及重複解碼方式. 採用代數解碼的Reed-Solomon code …

Method and apparatus for Viterbi detection of generalized partial response signals including two-way add/compare/select for improved channel speed

RD Cideciyan, JD Coker, ES Eleftheriou… - US Patent …, 2002 - Google Patents
PARTIAL MATCHED FILTER 108 two-way compare for comparing first and Second State
metric input values can include a hard shift for providing an add for the first State metric input …

[图书][B] High throughput VLSI architectures for iterative decoders

E Yeo - 2003 - search.proquest.com
This project addresses the algorithms for and implementations of iterative decoders for error
control in communication applications. The iterative codes are based on various …