[PDF][PDF] Implementation of transistor stacking technique in combinational circuits

A Nagar, V Parmar - IOSR Journal of VLSI and Signal Processing, 2014 - academia.edu
This paper deals with the reduction of power dissipation in the basic logic circuit like NAND
gate and NOR gate by using transistor stacking technique. The logic gates are designed …

Design of high speed and leakage tolerant CMOS comparator in UDSM technology

U Soni, A Vidyarthi, S Akashe - 2013 Third International …, 2013 - ieeexplore.ieee.org
In modern digital VLSI design, domino logic style circuits are widely used. The CMOS
domino logic circuit dissipates very low standby power and exhibits less area. We design a …

[PDF][PDF] Techniques for sub-threshold leakage reduction in low power cmos circuit designs

A Oza, P Kadam - International Journal of Computer Applications, 2014 - academia.edu
Power dissipation is a key consideration in the design of nano-scale CMOS VLSI circuits.
Various techniques have been proposed for reduction of leakage in CMOS transistors. As …

A rule-based method for minimizing power dissipation by reducing switching activity of digital circuits

S Das, S Ghosh, P Dasgupta, S Sensarma - 2015 - ir.iimcal.ac.in
Minimization of power dissipation of VLSI circuits is one of the major concerns of recent
digital circuit design primarily due to the ever decreasing feature sizes of circuits, higher …

Design and Analysis of Ultra-low Power Voltage Controlled Oscillator in Nanoscale Technologies

R Raghavendra, S Saxena - International Journal of …, 2024 - ijeer.forexjournal.co.in
In latest wired and wireless communication equipment, VCO (voltage-controlled oscillator) is
the major building block and particularly used as the stable high frequency clock generator …

[PDF][PDF] analysis & Desing of Two-Stage Operational Trans-conductance Amplifier

S Goswami - 2023 - 164.52.195.196
The operational trans-conductance amplifier (OTA) is an amplifier which has differential
input voltage for generating an output current. Hence OTA is control current source (VCCS) …

[PDF][PDF] Design of a Low Power SRAM Cell by Tanner Tool 45 NM

YS Parihar, G Jangid - International Journal on Recent and Innovation … - academia.edu
The absorption of power & SRAM's speed are major concern which followed several
designs in accordance to the minimal absorption of power. The main concern of this …

[PDF][PDF] A LEAKAGE TOLERANT CMOS COMPARATOR

S Goswami - ijeast.com
In digital VLSI design, domino logic style circuits are widely used. The domino of CMOS
logic circuit dissipates very low standby power and exhibits less area. We design a …

[PDF][PDF] Ultra-Low Power Stacked nMOS m-Sequence Code Generator with Reduced Leakage Power for Body Sensor Node Applications

SVRS Reddy, T Revanth, S Musala - SAMRIDDHI: A Journal of …, 2020 - smsjournals.com
Ultra-Low Power Stacked nMOS m-Sequence Code Generator with Reduced Leakage Power
for Body Sensor Node Applications Page 1 8989 SAMRIDDHI : A Journal of Physical Sciences …

[PDF][PDF] Design of Low Power CMOS Comparator in UDSM Technology

K Ravi - academia.edu
In modern digital VLSI design, domino logic style circuits are widely used. The CMOS
domino logic circuit dissipates very low standby power and exhibits less area. We design a …