Feeding hungry models less: Deep transfer learning for embedded memory PPA models: Special session
F Last, U Schlichtmann - 2021 ACM/IEEE 3rd Workshop on …, 2021 - ieeexplore.ieee.org
Supervised machine learning requires large amounts of labeled data for training. In power,
performance and area (PPA) estimation of embedded memories, every new memory …
performance and area (PPA) estimation of embedded memories, every new memory …
Partial sharing neural networks for multi-target regression on power and performance of embedded memories
F Last, U Schlichtmann - Proceedings of the 2020 ACM/IEEE Workshop …, 2020 - dl.acm.org
Memories contribute significantly to the overall power, performance and area (PPA) of
modern integrated electronic systems. Owing to their regular structure, memories are …
modern integrated electronic systems. Owing to their regular structure, memories are …
Training PPA Models for Embedded Memories on a Low-data Diet
F Last, U Schlichtmann - ACM Transactions on Design Automation of …, 2022 - dl.acm.org
Supervised machine learning requires large amounts of labeled data for training. In power,
performance, and area (PPA) estimation of embedded memories, every new memory …
performance, and area (PPA) estimation of embedded memories, every new memory …
Fast and Accurate PPA Modeling with Transfer Learning
L Francisco, P Franzon… - 2021 ACM/IEEE 3rd …, 2021 - ieeexplore.ieee.org
The power, performance, and area (PPA) of a System-on-Chip (SoC) is known only after a
months-long process. This process includes iterations over the architectural design, register …
months-long process. This process includes iterations over the architectural design, register …
Post-Layout Parasitic Capacitance Prediction Methodology Using Bayesian Optimization
G Kim, J Park, SO Jung - 2024 International Conference on …, 2024 - ieeexplore.ieee.org
In this paper, we proposed parasitic capacitance prediction methodology using Bayesian
optimization to accelerate the iterative design process. The layout process while circuit …
optimization to accelerate the iterative design process. The layout process while circuit …
Differentially Evolving Memory Ensembles: Pareto Optimization based on Computational Intelligence for Embedded Memories on a System Level
F Last, C Yeni, U Schlichtmann - 2022 27th Asia and South …, 2022 - ieeexplore.ieee.org
As the relative power, performance, and area (PPA) impact of embedded memories
continues to grow, proper parameterization of each of the thousands of memories on a chip …
continues to grow, proper parameterization of each of the thousands of memories on a chip …
[图书][B] Statistical Modeling of SRAMs
H Nichols - 2022 - search.proquest.com
Characterizing static random access memories (SRAMs) is difficult but necessary to
understand its properties. Choosing an optimal memory requires critical characteristics such …
understand its properties. Choosing an optimal memory requires critical characteristics such …
[引用][C] A Self-Learning Dynamic Memory Design Method
VS Melikyan, NE Mamikonyan - ՀՀ ԳԱԱ Տեղեկագիր: Տեխնիկական …, 2020 - ՀՀ ԳԱԱ