For parallelism to become tractable for mass programmers, shared-memory languages and
environments must evolve to enforce disciplined practices that ban" wild shared-memory …

A key challenge in architecting a CMP with many cores is maintaining cache coherence in
an efficient manner. Directory-based protocols avoid the bandwidth overhead of snoop …

The prevalence of multicore architectures has accentuated the need for scalable cache
coherence solutions. Many of the proposed designs use a mix of 1-to-1, 1-to-many (1-to-M) …

In this paper, we evaluate a set of coherence architectures in the context of a 1024-core chip
multiprocessor (CMP) tailored to throughput-oriented parallel workloads. Based on our …

Although snoop-based coherence protocols provide fast cache-to-cache transfers with a
simple and robust coherence mechanism, scaling the protocols has been difficult due to the …

This paper advocates Atomic Coherence, a framework that simplifies cache coherence
protocol specification, design, and verification by decoupling races from the protocol's …

Two broad classes of memory models are available today: models with hardware cache
coherence, used in conventional chip multiprocessors, and models that rely upon software …

Embedded devices are becoming more and more present everywhere. Moreover mobile
devices are becoming also more computationally powerful. These embedded architectures …

Manycore processors, with tens to hundreds of tiny cores but no hardware-based cache
coherence, can offer tremendous peak throughput on highly parallel programs while being …

In chip multiprocessors (CMPs), maintaining cache coherence can account for a major
performance overhead. Write-invalidate protocols adapted by most CMPs generate high …