Two equalizer filter topologies and a merged equalizer/CDR circuit are described that
operate at 10 Gb/s in 0.13-mum CMOS technology. Using techniques such as reverse …

A fully-integrated 60-GHz transceiver system with on-board antenna assembly is presented.
Incorporating on-off keying (OOK) and low-cost antenna designs, this prototype …

An adaptive equalizer incorporates spectrum-balancing technique to achieve high speed
and low power dissipation. Obviating the need for slicers, this circuit compares the low and …

A transceiver capable of 6.25-Gb/s data transmission across legacy communications
equipment backplanes is described. To achieve a bit error rate (BER)< 10/sup-15/, transmit …

A 10Gb/s CMOS adaptive equalizer for backplane applications Page 1 328 • 2005 IEEE
International Solid-State Circuits Conference 0-7803-8904-2/05/$20.00 ©2005 IEEE. ISSCC …

A 7-tap 40 Gb/s FFE using a 65 nm standard CMOS process is described. A number of
broadbanding and calibration techniques are used, which allow high-speed operation while …

This paper describes a 20-Gb/s continuous-time adaptive passive equalizer utilizing on-chip
lumped RLC components. Passive equalizers offer the advantages of higher bandwidth and …

A quarter-rate sampling receiver with a 2-tap decision feedback equalizer (DFE) is
implemented in 90-nm CMOS technology for low-power I/O links. An analog sampling and …

A merged equalizer/CDR circuit employs a parallel-path equalizer and triple-loop adaptation
to achieve a binary data rate of 10 Gb/s. Realized in 0.13 μm CMOS technology, the circuit …

In this tutorial paper we present equalization techniques to mitigate inter-symbol interference
(ISI) in high-speed communication links. Both transmit and receive equalizers are analyzed …