Probabilistic model checking: Advances and applications

M Kwiatkowska, G Norman, D Parker - … System Verification: State-of the-Art …, 2018 - Springer
Probabilistic model checking is a powerful technique for formally verifying quantitative
properties of systems that exhibit stochastic behaviour. Such systems are found in many …

The emperor's new security indicators

SE Schechter, R Dhamija, A Ozment… - 2007 IEEE Symposium …, 2007 - ieeexplore.ieee.org
We evaluate Website authentication measures that are designed to protect users from man-
in-the-middle,'phishing', and other site forgery attacks. We asked 67 bank customers to …

Accurate reliability evaluation and enhancement via probabilistic transfer matrices

S Krishnaswamy, GF Viamontes… - … Automation and Test …, 2005 - ieeexplore.ieee.org
Soft errors are an increasingly serious problem for logic circuits. To estimate the effects of
soft errors on such circuits, we develop a general computational framework based on …

PROPhESY: A PRObabilistic ParamEter SYnthesis Tool

C Dehnert, S Junges, N Jansen, F Corzilius… - … Aided Verification: 27th …, 2015 - Springer
We present PROPhESY, a tool for analyzing parametric Markov chains (MCs). It can
compute a rational function (ie, a fraction of two polynomials in the model parameters) for …

A stochastic computational approach for accurate and efficient reliability evaluation

J Han, H Chen, J Liang, P Zhu, Z Yang… - IEEE Transactions on …, 2012 - ieeexplore.ieee.org
Reliability is fast becoming a major concern due to the nanometric scaling of CMOS
technology. Accurate analytical approaches for the reliability evaluation of logic circuits …

Reliability evaluation of logic circuits using probabilistic gate models

J Han, H Chen, E Boykin, J Fortes - Microelectronics Reliability, 2011 - Elsevier
Logic circuits built using nanoscale technologies have significant reliability limitations due to
fundamental physical and manufacturing constraints of their constituent devices. This paper …

The future of integrated circuits: A survey of nanoelectronics

M Haselman, S Hauck - Proceedings of the IEEE, 2009 - ieeexplore.ieee.org
While most of the electronics industry is dependent on the ever-decreasing size of
lithographic transistors, this scaling cannot continue indefinitely. Nanoelectronics (circuits …

Probabilistic transfer matrices in symbolic reliability analysis of logic circuits

S Krishnaswamy, GF Viamontes, IL Markov… - ACM Transactions on …, 2008 - dl.acm.org
We propose the probabilistic transfer matrix (PTM) framework to capture nondeterministic
behavior in logic circuits. PTMs provide a concise description of both normal and faulty …

Toward hardware-redundant, fault-tolerant logic for nanoelectronics

J Han, J Gao, P Jonker, Y Qi… - IEEE Design & Test of …, 2005 - ieeexplore.ieee.org
This article provides an overview of several logic redundancy schemes, including von
Neumann's multiplexing logic, N-tuple modular redundancy, and interwoven redundant …

Evaluating the reliability of NAND multiplexing with PRISM

G Norman, D Parker, M Kwiatkowska… - IEEE Transactions on …, 2005 - ieeexplore.ieee.org
Probabilistic-model checking is a formal verification technique for analyzing the reliability
and performance of systems exhibiting stochastic behavior. In this paper, we demonstrate …