[PDF][PDF] Array multiplier using XNOR-XOR Cell
R Garg, S Nehra, BP Singh - International Journal of Engineering Science …, 2013 - Citeseer
The multipliers are the key structure for designing high performance digital systems. Design
considerations of multiplier include high speed, less power consumption, less PDP (power …
considerations of multiplier include high speed, less power consumption, less PDP (power …
[PDF][PDF] Low Power 10T XOR based 1 Bit Full Adder
DS Chandel, S Bandewar, AK Singh - International Journal of Computer …, 2015 - Citeseer
The popularity and necessity of portable electronic systems by users have strongly
influenced VLSI designers to make great effort for reduced silicon area, improved speeds …
influenced VLSI designers to make great effort for reduced silicon area, improved speeds …
FPGA Implementation of High Speed Hardware Efficient Carry Select Adder
S Saravanakumar, V Vijeyakumar… - International Journal …, 2018 - search.proquest.com
This paper presents a novel architecture for high speed and hardware efficient carry select
addition. We modify the two operand ripple carry addition followed in conventional Carry …
addition. We modify the two operand ripple carry addition followed in conventional Carry …
[PDF][PDF] Implementation of Energy-Efficient Low Power 10T Full-Adder
K Babulu, GV Ujwala - Citeseer
In this Paper, the performance of 10-tranistor based full adder is analyzed and compared
with that of two different types of full adder based on Swing Restored Complementary pass …
with that of two different types of full adder based on Swing Restored Complementary pass …