An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/A converter
An 800-MHz low-power direct digital frequency synthesizer (DDFS) with an on-chip digital-to-
analog (D/A) converter is presented. The DDFS consists of a phase accumulator, two phase …
analog (D/A) converter is presented. The DDFS consists of a phase accumulator, two phase …
Phase to sinusoid amplitude conversion techniques for direct digital frequency synthesis
JMP Langlois, D Al-Khalili - IEE Proceedings-Circuits, Devices and Systems, 2004 - IET
The authors present a review of phase to sine amplitude conversion (PSAC) techniques for
direct digital frequency synthesis (DDFS). Principles of DDFS are first considered, then …
direct digital frequency synthesis (DDFS). Principles of DDFS are first considered, then …
Considerations for phase accumulator design for direct digital frequency synthesizers
DJ Betowski, V Beiu - International Conference on Neural …, 2003 - ieeexplore.ieee.org
This paper reviews the approach of using a direct digital frequency synthesizer (DDFS) to
generate high-resolution, fast switching frequencies for modern communication systems …
generate high-resolution, fast switching frequencies for modern communication systems …
A 12-bit nonlinear DAC for direct digital frequency synthesis
Z Zhou, GS La Rue - … Transactions on Circuits and Systems I …, 2008 - ieeexplore.ieee.org
A 12-bit nonlinear digital-to-analog converter (DAC) was fabricated in a 0.35-mum SOI
CMOS process. The nonlinear DAC can implement a piecewise-linear approximation to a …
CMOS process. The nonlinear DAC can implement a piecewise-linear approximation to a …
Low power pipeline-parallel phase accumulator
MC Parameshwara, A Khan - International Journal of Information …, 2022 - Springer
In this brief, a low power pipeline-parallel phase accumulator (PPA) with 32-bit frequency
resolution and 10-bit phase resolution is proposed for direct digital frequency synthesizer …
resolution and 10-bit phase resolution is proposed for direct digital frequency synthesizer …
Hardware optimized direct digital frequency synthesizer architecture with 60 dBc spectral purity
JMP Langlois, D Al-Khalili - 2002 IEEE International …, 2002 - ieeexplore.ieee.org
We introduce a novel sine-output Direct Digital Frequency Synthesizer (DDFS) architecture,
optimized for hardware implementation, that achieves better than 60 dBc spectral purity from …
optimized for hardware implementation, that achieves better than 60 dBc spectral purity from …
GMSK modulator for GSM system, an economical implementation on FPGA
KMN Babu, KK Vinaymurthi - 2011 International Conference on …, 2011 - ieeexplore.ieee.org
This paper demonstrates an economical implementation of Gaussian Minimum shift keying
(GMSK) modulator for Global System for Mobile communication (GSM) system using the …
(GMSK) modulator for Global System for Mobile communication (GSM) system using the …
Area-optimized implementation of quadrature direct digital frequency synthesizers on LUT-based FPGAs
F Cardells-Tormo… - IEEE Transactions on …, 2003 - ieeexplore.ieee.org
This paper deals with an field-programmable gate array (FPGA)-implementation of
quadrature direct digital frequency synthesizers (QDDFS), and, in particular, with those …
quadrature direct digital frequency synthesizers (QDDFS), and, in particular, with those …
The application of a novel direct digital frequency synthesizer for the IP core design of all digital three phase SPWM generator
L Yi, Y Yuan, Y Ningmei, G Yong - The 4th International Power …, 2004 - ieeexplore.ieee.org
This work presents a novel method based on direct digital frequency synthesizer (DDS or
DDFS) for all digital three phase SPWM generator IP core, which is improved from …
DDFS) for all digital three phase SPWM generator IP core, which is improved from …