Hardware Circuits and Systems Design for Post-Quantum Cryptography–A Tutorial Brief
Due to the increasing threats from possible large-scale quantum computers, post-quantum
cryptography (PQC) has drawn significant attention from various communities recently. In …
cryptography (PQC) has drawn significant attention from various communities recently. In …
A hybrid SRAM/RRAM in-memory computing architecture based on a reconfigurable SRAM sense amplifier
In this paper, a hybrid memory architecture based on a new array of SRAM and resistive
random-access memory (RRAM) cells is proposed to perform in-memory computing by …
random-access memory (RRAM) cells is proposed to perform in-memory computing by …
CapCAM: A multilevel capacitive content addressable memory for high-accuracy and high-scalability search and compute applications
As one type of associative memory, content-addressable memory (CAM) has become a
critical component in several applications, including caches, routers, and pattern matching …
critical component in several applications, including caches, routers, and pattern matching …
A look-up table-based processing-in-SRAM architecture for energy-efficient search applications
This paper presents an efficient in-memory computing architecture for search and logic
function applications. The proposed design benefits from an SRAM cell, using two single …
function applications. The proposed design benefits from an SRAM cell, using two single …
Local bit line 8T SRAM based in-memory computing architecture for energy-efficient linear error correction codec implementation
AK Rajput, M Pattanaik - Microelectronics Journal, 2023 - Elsevier
Memory reliability is a critical issue in SRAM-based In-Memory Computing (IMC)
architecture. The rapid advance in transistor technology makes SRAM more sensitive to soft …
architecture. The rapid advance in transistor technology makes SRAM more sensitive to soft …
In Situ Storing 8T SRAM-CIM Macro for Full-Array Boolean Logic and Copy Operations
Computing in-memory (CIM) is a promising new computing method to solve problems
caused by von Neumann bottlenecks. It mitigates the need for transmitting large amounts of …
caused by von Neumann bottlenecks. It mitigates the need for transmitting large amounts of …
Local bit-line shared pass-gate 8T SRAM based energy efficient and reliable In-Memory Computing architecture
Abstract The In-Memory Computing (IMC) architecture based on Conventional 6T, 8T, and
10T SRAM suffers from compute disturbance, compute-failure, and half-select issues, which …
10T SRAM suffers from compute disturbance, compute-failure, and half-select issues, which …
A Reliable and High-Speed 6T Compute-SRAM Design With Dual-Split-VDD Assist and Bitline Leakage Compensation
Y Wang, S Zhang, Y Li, J Chen… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Compute SRAM (CSRAM) can be configured to execute efficient in-memory logic
computation and search operations, which is made possible by the multirow activation …
computation and search operations, which is made possible by the multirow activation …
Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)
D Challagundla, I Bezzam, R Islam - arXiv preprint arXiv:2411.09546, 2024 - arxiv.org
While general-purpose computing follows Von Neumann's architecture, the data movement
between memory and processor elements dictates the processor's performance. The …
between memory and processor elements dictates the processor's performance. The …
A 10T SRAM with two read and write modes across row and column for CAM operation and computing in-memory
Z Zhang, Z Chen, S Chen, G Xie… - … Symposium on Circuits …, 2024 - ieeexplore.ieee.org
With SRAM-based computing in-memory (CIM), parallel searching is implemented through
the multi-row activation scheme, which necessitates words to be stored in the column-wise …
the multi-row activation scheme, which necessitates words to be stored in the column-wise …