FPGA acceleration on a multi-layer perceptron neural network for digit recognition

I Westby, X Yang, T Liu, H Xu - The Journal of Supercomputing, 2021 - Springer
This paper proposes field-programmable gate array (FPGA) acceleration on a scalable multi-
layer perceptron (MLP) neural network for classifying handwritten digits. First, an …

FPGA Implementation of Complex-Valued Neural Network for Polar-Represented Image Classification

M Ahmad, L Zhang, MEH Chowdhury - Sensors, 2024 - mdpi.com
This proposed research explores a novel approach to image classification by deploying a
complex-valued neural network (CVNN) on a Field-Programmable Gate Array (FPGA) …

A power-efficient optimizing framework FPGA accelerator for YOLO

S Li, C Yu, T Xie, W Feng - 2022 15th International Congress on …, 2022 - ieeexplore.ieee.org
Due to the high parallelism and efficiency, Convolution acceleration and buffer pipeline
architecture are common solutions for convolutional neural network (CNN) acceleration …

An FPGA-based accelerator for deep neural network with novel reconfigurable architecture

H Jia, D Ren, X Zou - IEICE Electronics Express, 2021 - jstage.jst.go.jp
Due to the high parallelism, Data flow architecture is a common solution for deep neural
network (DNN) acceleration, however, existing DNN accelerate solutions exhibit limited …

Parameterizable Design on Convolutional Neural Networks Using Chisel Hardware Construction Language

MC Madineni, M Vega, X Yang - Micromachines, 2023 - mdpi.com
This paper presents a parameterizable design generator on convolutional neural networks
(CNNs) using the Chisel hardware construction language (HCL). By parameterizing …

An energy-efficient FPGA-based convolutional neural network implementation

H Irmak, N Alachiotis, D Ziener - 2021 29th Signal Processing …, 2021 - ieeexplore.ieee.org
Convolutional Neural Networks (CNNs) are a very popular class of artificial neural networks.
Current CNN models provide remarkable performance and accuracy in image processing …

Mixed-precision weights network for field-programmable gate array

N Fuengfusin, H Tamukoh - PloS one, 2021 - journals.plos.org
In this study, we introduced a mixed-precision weights network (MPWN), which is a
quantization neural network that jointly utilizes three different weight spaces: binary {− 1, 1} …

A runtime programmable accelerator for convolutional and multilayer perceptron neural networks on fpga

E Kabir, A Poudel, Z Aklah, M Huang… - … Symposium on Applied …, 2022 - Springer
Deep neural networks (DNNs) are prevalent for many applications related to classification,
prediction and regression. To perform different applications with better performance and …

Reducing OpenMP to FPGA round-trip times with predictive modelling

J Brandner, F Mayer, M Philippsen - International Workshop on OpenMP, 2022 - Springer
Recent works aimed at expanding the target offloading capabilities of OpenMP to FPGA
platforms. While enabling the easy construction of heterogeneous systems, the approach …

Lightweight Neural Network Architectures for Resource-Limited Devices

AL Reed, X Yang, S Sha - 2022 23rd International Symposium …, 2022 - ieeexplore.ieee.org
This paper presents a scalable design architecture for lightweight neural networks for
resource-limited devices. As case studies, several field-programmable gate array (FPGA) …