As von Neumann computing architectures become increasingly constrained by data-
movement overheads, researchers have started exploring in-memory computing (IMC) …

This paper presents a 4+ 2T SRAM for embedded searching and in-memory-computing
applications. The proposed SRAM cell uses the n-well as the write wordline to perform write …

A fully integrated switched capacitor voltage regulator (SCVR) with on-die high density MIM
capacitor, distributed across a 14 KB register file (RF) load is demonstrated in 22 nm tri-gate …

Multiported high-performance on-die memories occupy significantly more die area than a
comparable single-port memory. Among various multiport memory topologies, the 1-read …

This paper presents a novel 9T static random access memory (SRAM) cell consisting of a
single ended isolated read bit line with 2T read port for improving stability and a tail …

The demand for high-performance graphics capability even in extremely power-constrained
platforms such as smartphones and tablets requires circuit techniques that scale from …

In high performance computing (HPC) applications, the speed of the L1 cache will typically
determine the maximum frequency (/Max) of the processor core. Companies that mass …

An optimized co-design of SRAM cell, assist schemes, and layout is proposed to achieve
wide voltage range operation of SRAM from 0.35-1.2 V at all process corners. A differential …

In this paper, we characterize the interplay between power consumption and performance of
a matchline-based Content Addressable Memory and then propose the use of a multi-Vdd …

System-on-Chip (SoC) designs contain a variety of IP blocks which use multiport memories
to improve performance by enabling multiple simultaneous operations in the same memory …