Scaling aligned carbon nanotube transistors to a sub-10 nm node

Y Lin, Y Cao, S Ding, P Zhang, L Xu, C Liu, Q Hu… - Nature …, 2023 - nature.com
Aligned semiconducting carbon nanotubes are a potential alternative to silicon in the
creation of scaled field-effect transistors (FETs) due to their easy miniaturization and high …

Carbon nanotube electronics for IoT sensors

JA Cardenas, JB Andrews, SG Noyce… - Nano Futures, 2020 - iopscience.iop.org
Abstract The Internet of Things (IoT) is the concept of a ubiquitous computing ecosystem in
which electronics of custom form factors are seamlessly embedded into everyday objects. At …

Radiofrequency transistors based on aligned carbon nanotube arrays

H Shi, L Ding, D Zhong, J Han, L Liu, L Xu, P Sun… - Nature …, 2021 - nature.com
The development of next-generation wireless communication technology requires integrated
radiofrequency devices capable of operating at frequencies greater than 90 GHz. Carbon …

Complementary transistors based on aligned semiconducting carbon nanotube arrays

C Liu, Y Cao, B Wang, Z Zhang, Y Lin, L Xu, Y Yang… - ACS …, 2022 - ACS Publications
High-density semiconducting aligned carbon nanotube (A-CNT) arrays have been
demonstrated with wafer-scale preparation of materials and have shown high performance …

Gigahertz integrated circuits based on carbon nanotube films

D Zhong, Z Zhang, L Ding, J Han, M Xiao, J Si, L Xu… - Nature …, 2018 - nature.com
Progress in the controlled synthesis and post-growth treatment of carbon nanotubes has led
to the fabrication of nanotube-based field-effect transistors with intrinsic performance close …

Evaluation of the Raw microprocessor: An exposed-wire-delay architecture for ILP and streams

MB Taylor, W Lee, J Miller, D Wentzlaff, I Bratt… - ACM SIGARCH …, 2004 - dl.acm.org
This paper evaluates the Raw microprocessor. Raw addresses thechallenge of building a
general-purpose architecture that performswell on a larger class of stream and embedded …

New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation

Y Cao, T Sato, M Orshansky… - Proceedings of the …, 2000 - ieeexplore.ieee.org
A new paradigm of predictive MOSFET and interconnect modeling is introduced. This
approach is developed to specifically address SPICE compatible parameters for future …

The implementation of the Itanium 2 microprocessor

SD Naffziger, G Colon-Bonet, T Fischer… - IEEE Journal of Solid …, 2002 - ieeexplore.ieee.org
This 64-b microprocessor is the second-generation design of the new Itanium architecture,
termed explicitly parallel instruction computing (EPIC). The design seeks to extract maximum …

[图书][B] Low-power electronics design

C Piguet - 2018 - books.google.com
The power consumption of integrated circuits is one of the most problematic considerations
affecting the design of high-performance chips and portable devices. The study of power …

The future of interconnection technology

TN Theis - IBM Journal of Research and Development, 2000 - ieeexplore.ieee.org
Continuing advances in interconnection technology are seen as essential to continued
improvements in integrated circuit performance. The recent introduction of copper …