Benchmark figure of merit extensions for low jitter phase locked loops inspired by new PLL architectures
W Bae - IEEE Access, 2022 - ieeexplore.ieee.org
A conventional figure-of-merit (FOM) for a phase-locked loop (PLL) has served as the most
powerful indicator to compare and to normalize performance of different PLL designs …
powerful indicator to compare and to normalize performance of different PLL designs …
A low-jitter ring-oscillator phase-locked loop using feedforward noise cancellation with a sub-sampling phase detector
Ring-oscillator (RO)-based phase-locked loops (PLLs) are very attractive for system-on-chip
applications for their compactness and tuning range, but suffer from high jitter and supply …
applications for their compactness and tuning range, but suffer from high jitter and supply …
A low-jitter and low-reference-spur ring-VCO-based switched-loop filter PLL using a fast phase-error correction technique
A low-jitter and low-reference-spur ring-type voltage-controlled oscillator (VCO)-based
switched-loop filter (SLF) phase-locked loop (PLL) is presented. To enhance the capability …
switched-loop filter (SLF) phase-locked loop (PLL) is presented. To enhance the capability …
A 2.4-GHz 1.5-mW digital multiplying delay-locked loop using pulsewidth comparator and double injection technique
H Kim, Y Kim, T Kim, HJ Ko… - IEEE Journal of Solid-State …, 2017 - ieeexplore.ieee.org
In this paper, we propose a low-jitter low-power digital multiplying delay-locked loop (MDLL)
with a self-calibrated double reference injection scheme. To reduce jitter, the noisy edge of …
with a self-calibrated double reference injection scheme. To reduce jitter, the noisy edge of …
An 82–107.6-GHz Integer- ADPLL Employing a DCO With Split Transformer and Dual-Path Switched-Capacitor Ladder and a Clock-Skew-Sampling Delta–Sigma …
A W-band integer-N all-digital phase-locked loop (ADPLL) aiming for wide frequency tuning
range (TR) and low phase noise is proposed. The W-band ADPLL employs a digitally …
range (TR) and low phase noise is proposed. The W-band ADPLL employs a digitally …
19.4 A 0.0049 mm2 2.3 GHz sub-sampling ring-oscillator PLL with time-based loop filter achieving− 236.2 dB jitter-FOM
J Chuang, H Krishnaswamy - 2017 IEEE International Solid …, 2017 - ieeexplore.ieee.org
High-performance phase-locked loops (PLLs) and clock multipliers with low jitter/phase
noise are essential for numerous applications, such as digital microprocessors and SoCs …
noise are essential for numerous applications, such as digital microprocessors and SoCs …
A 0.5 V-to-0.9 V 0.2 GHz-to-5GHz ultra-low-power digitally-assisted analog ring PLL with less than 200ns lock time in 22nm FinFET CMOS technology
B Xiang, Y Fan, J Ayers, J Shen… - 2020 IEEE custom …, 2020 - ieeexplore.ieee.org
This paper presents an ultra-low power digitally-assisted analog ring phase-locked loop
(PLL) with a tunable switched capacitor loop filter. The PLL achieves a power efficiency of …
(PLL) with a tunable switched capacitor loop filter. The PLL achieves a power efficiency of …
A Time-Interleaved Ring-VCO with Reduced 1/ Phase Noise Corner, Extended Tuning Range and Inherent Divided Output
This paper describes a time-interleaved (TI) ring-VCO (RVCO) exhibiting an improved phase
noise over a wide range of frequency offsets, an extended tuning range and an inherent …
noise over a wide range of frequency offsets, an extended tuning range and an inherent …
A− 236.3 dB FoM sub-sampling low-jitter supply-robust ring-oscillator PLL for clocking applications with feed-forward noise-cancellation
A 2-2.8 GHz 65nm CMOS ring oscillator PLL occupies an active area of 0.022 mm 2,
consumes 5.86 mW and achieves a 633fs RMS jitter at 2.36 GHz and an FOM jitter of-236.3 …
consumes 5.86 mW and achieves a 633fs RMS jitter at 2.36 GHz and an FOM jitter of-236.3 …
Reference spur reduction techniques for a phase-locked loop
This paper presents the reference spur reduction techniques for an analog phase-locked
loop (PLL). A simple leakage compensation loop is proposed, which cancels the leakage …
loop (PLL). A simple leakage compensation loop is proposed, which cancels the leakage …