Semiconductor structure including a suspended membrane containing a central segment of structured thickness
A semiconductor structure including a semiconductor layer made of a crystalline
semiconductor compound, a portion of the semiconductor layer which forms a suspended …
semiconductor compound, a portion of the semiconductor layer which forms a suspended …
Process for producing a strained layer based on germanium-tin
V Reboud, JM Hartmann, A Tchelnokov… - US Patent …, 2020 - Google Patents
The invention pertains to a process for producing a strained layer based on germanium-tin
(GeSn). The process includes a step of producing a semiconductor stack containing a layer …
(GeSn). The process includes a step of producing a semiconductor stack containing a layer …
Shadow trim line edge roughness reduction
TA Kamp, RP Belen - US Patent 9,711,359, 2017 - Google Patents
A method for etching an etch layer in a stack over a substrate wherein the etch layer is under
a mask layer which is under a patterned organic mask is provided. The stack and substrate …
a mask layer which is under a patterned organic mask is provided. The stack and substrate …
SiGeSn laser diodes and method of fabricating same
A laser diode including a double heterostructure comprising a top layer, a buffer layer
formed on a substrate, and an intrinsic active layer formed between the top layer and the …
formed on a substrate, and an intrinsic active layer formed between the top layer and the …
Method for the nanoscale etching of a germanium-tin alloy (GeSn) for a FET transistor
E Eustache, B Salem, JM Hartmann, F Bassani… - US Patent …, 2022 - Google Patents
(57) ABSTRACT A method for the nanoscale etching of a layer of Ge1-Sn, on a carrier for a
FET transistor, x being the concentration of tin in the GeSn alloy, the etching method …
FET transistor, x being the concentration of tin in the GeSn alloy, the etching method …