Opportunities and challenges of tunnel FETs
Sustaining of Moore's Law over the next decade will require not only continued scaling of
the physical dimensions of transistors but also performance improvement and aggressive …
the physical dimensions of transistors but also performance improvement and aggressive …
Subthreshold performance of in 1–x Ga x as based dual metal with gate stack cylindrical/surrounding gate nanowire MOSFET for low power analog applications
In this paper, In 1–x Ga x As based Dual Metal with Gate Stack Cylindrical/Surrounding Gate
Nanowire MOSFET (DMGS CG/SG NWFET) has been proposed for the first time to achieve …
Nanowire MOSFET (DMGS CG/SG NWFET) has been proposed for the first time to achieve …
In0.53Ga0.47As FinFET and GAA-FET With Remote-Plasma Treatment
QH Luc, KS Yang, JW Lin, CC Chang… - IEEE Electron …, 2018 - ieeexplore.ieee.org
This letter presents a remote NH 3/N 2 plasma treatment after gate oxide deposition for
improving the electrical characteristics and the reliability of In 0.53 Ga 0.47 As FinFET. The …
improving the electrical characteristics and the reliability of In 0.53 Ga 0.47 As FinFET. The …
Effect of varying Indium concentration of InGaAs channel on device and circuit performance of nanoscale double gate heterostructure MOSFET
The detailed numerical analysis is performed to study and evaluate the impact of Indium (In)
concentrations of the Indium gallium arsenide (InGaAs) channel on different device …
concentrations of the Indium gallium arsenide (InGaAs) channel on different device …
III-V Devices and technology for CMOS
N Waldron - High Mobility Materials for CMOS Applications, 2018 - Elsevier
In this chapter, advances in the use of III-V materials for both n-and p-MOSFET devices will
be reviewed including progress in gate stack technology and its associated reliability. For …
be reviewed including progress in gate stack technology and its associated reliability. For …
Extensive assessment of the charge-trapping kinetics in InGaAs MOS gate-stacks for the demonstration of improved BTI reliability
Gate-stack reliability has been a major roadblock in the realization of InGaAs-channel based
logic technology. Excessive charge trapping in the gate-oxide causes time-dependent drift in …
logic technology. Excessive charge trapping in the gate-oxide causes time-dependent drift in …
Size-effects in indium gallium arsenide nanowire field-effect transistors
We fabricate and analyze InGaAs nanowire MOSFETs with channel widths down to 18 nm.
Low-temperature measurements reveal quantized conductance due to subband splitting, a …
Low-temperature measurements reveal quantized conductance due to subband splitting, a …
Electrical Analysis and PBTI Reliability of In0.53Ga0.47As MOSFETs With AlN Passivation Layer and NH3 Postremote Plasma Treatment
PC Chang, QH Luc, YC Lin, SC Liu… - … on Electron Devices, 2016 - ieeexplore.ieee.org
We report a notable improvement in performance, electron transport, and reliability of HfO
2/In 0.53 Ga 0.47 As nMOSFETs using a plasma-enhanced atomic layer deposition AlN …
2/In 0.53 Ga 0.47 As nMOSFETs using a plasma-enhanced atomic layer deposition AlN …
Switching Performance Analysis of III-V FinFETs
During the last decades, the field-effect transistor technology has changed at an amazing
rate and improved its performance gradually. Mostly utilized transistor technology has been …
rate and improved its performance gradually. Mostly utilized transistor technology has been …
Impact of varying carbon concentration in SiC S/D asymmetric dual-k spacer for high performance and reliable FinFET
We propose a reliable asymmetric dual-k spacer with SiC source/drain (S/D) pocket as a
stressor for a Si channel. This enhances the device performance in terms of electron mobility …
stressor for a Si channel. This enhances the device performance in terms of electron mobility …