{D-Helix}: A Generic Decompiler Testing Framework Using Symbolic Differentiation

M Zou, A Khan, R Wu, H Gao, A Bianchi… - 33rd USENIX Security …, 2024 - usenix.org
Decompilers, one of the widely used security tools, transform low-level binary programs
back into their high-level source representations, such as C/C++. While state-of-the-art …

Correct-by-construction design of custom accelerator microarchitectures

J Yang, Z Yang, J Casas, S Ray - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Modern application-specific System-on-Chip designs include a variety of accelerator blocks
that customize microcontrollers with domain-specific instruction sets and optimized …

Equivalence checking of scheduling in high-level synthesis using deep state sequences

J Hu, G Wang, G Chen, X Wei - IEEE Access, 2019 - ieeexplore.ieee.org
By using high-level synthesis tools, electronic system level design provides a promising
solution to fill the growing design productivity gap of high quality hardware systems …

Automatic generation of high-coverage tests for RTL designs using software techniques and tools

Y Zhang, W Feng, M Huang - 2016 IEEE 11th Conference on …, 2016 - ieeexplore.ieee.org
Register Transfer Level (RTL) design validation is a crucial stage in the hardware design
process. We present a new approach to enhancing RTL design validation using available …

Scalable certification framework for behavioral synthesis front-end

Z Yang, K Hao, K Cong, L Lei, S Ray, F Xie - Proceedings of the 51st …, 2014 - dl.acm.org
Behavioral synthesis entails application of a sequence of transformations to compile a high-
level description of a hardware design (eg, in C/C++/SystemC) into a register-transfer level …

Regression testing of virtual prototypes using symbolic execution

B Lin, D Qian - arXiv preprint arXiv:1601.05850, 2016 - arxiv.org
Recently virtual platforms and virtual prototyping techniques have been widely applied for
accelerating software development in electronics companies. It has been proved that these …

Formally analyzing fault tolerance in datapath designs using equivalence checking

P Behnam, B Alizadeh, S Taheri… - 2016 21st Asia and …, 2016 - ieeexplore.ieee.org
In this paper, we present an efficient formal approach to check the equivalence of
synthesized Register Transfer Level (RTL) against the high level specification in the …

An Equivalence Checking Framework for Agile Hardware Design

Y Wang, F Xie, Z Yang, P Cocchini, J Yang - … of the 28th Asia and South …, 2023 - dl.acm.org
Agile hardware design enables designers to produce new design iterations efficiently.
Equivalence checking is critical in ensuring that a new design iteration conforms to its …

[PDF][PDF] SoC 高级综合验证研究进展

胡健, 胡永扬, 王观武, 陈桂林, 杨海涛, 康云… - 计算机辅助设计与图形学 …, 2021 - jcad.cn
针对近年来片上系统(system on chip, SoC) 高级综合验证领域的工作, 首先分析了高级综合验证
的难点, 然后根据应用领域将算法分为3 类: 高级综合前端验证算法, 高级综合调度验证算法和 …

Automated Verification of Compiler Transformations

Y Wang - 2024 - search.proquest.com
The ever-growing complexity of software and its target hardware makes it increasingly
challenging to develop reliable compilers that preserve the semantics of source code during …