LM Gupta, RG Hathorn, J Hayward… - US Patent …, 2021 - Google Patents
A computational device receives an indication of a minimum retention time in a cache for a plurality of tracks of an application. In response to determining that tracks of the application …
LM Gupta, KA Anderson, J Hayward… - US Patent …, 2021 - Google Patents
A minimum retention time in cache is indicated for a first plurality of tracks, where no minimum retention time is indicated for a second plurality of tracks. A cache management …
LM Gupta, RG Hathorn, J Hayward… - US Patent …, 2022 - Google Patents
A computational device receives an indication of a minimum retention time in a cache for a plurality of tracks of an application. In response to determining that tracks of the application …
D He, DA Palmer - US Patent 11,556,479, 2023 - Google Patents
Methods, systems, and devices for cache block budgeting techniques are described. In some memory systems, a controller may configure a memory device with a cache. The …
CC Coats, HU Darbaz - US Patent 11,144,476, 2021 - Google Patents
An apparatus includes a cache controller circuit and a multi-ported cache memory including a plurality of cache ways. The cache controller circuit is configured to maintain rank values …
LM Gupta, J Hayward, KA Anderson… - US Patent …, 2022 - Google Patents
A computational device receives indications of a minimum retention time and a maximum retention time in cache for a first plurality of tracks, wherein no indications of a minimum …
LM Gupta, J Hayward, KA Anderson… - US Patent …, 2021 - Google Patents
A computational device receives an indication that specifies a maximum retention time in cache for a first plurality of tracks, wherein no maximum retention time is specified for a …
LM Gupta, J Hayward, KA Anderson… - US Patent …, 2021 - Google Patents
A computational device receives indications of a minimum retention time and a maximum retention time in cache for a first plurality of tracks, wherein no indications of a minimum …