Design and VLSI implementation of pipelined multiply accumulate unit
In the majority of the Digital signal processing (DSP) applications, the critical operations
usually involve many multiplications and/or accumulations. So, for real time signal …
usually involve many multiplications and/or accumulations. So, for real time signal …
MIMO-OFDM LTE system based on a parallel IFFT/FFT on NoC-based FPGA
The growing demand for wireless devices capable of performing complex communication
processes has imposed an urgent need for high-speed communication systems and …
processes has imposed an urgent need for high-speed communication systems and …
ASIP approach for implementation of H. 264/AVC
This paper presents an Application-Specific Instruction Set Processor (ASIP) approach for
implementation of H. 264/AVC. The proposed ASIP has special instructions for intra …
implementation of H. 264/AVC. The proposed ASIP has special instructions for intra …
An area efficient real-and complex-valued multiply-accumulate SIMD unit for digital signal processors
L Gerlach, G Payá-Vayá… - 2015 IEEE Workshop on …, 2015 - ieeexplore.ieee.org
This paper explores a real-and complex-valued multiply-accumulate (MAC) functional unit
for digital signal processors. MAC units with single-instruction-multiple-data (SIMD) support …
for digital signal processors. MAC units with single-instruction-multiple-data (SIMD) support …
Bit manipulation accelerator for communication systems digital signal processor
SH Jeong, MH Sunwoo, SK Oh - EURASIP Journal on Advances in Signal …, 2005 - Springer
This paper proposes application-specific instructions and their bit manipulation unit (BMU),
which efficiently support scrambling, convolutional encoding, puncturing, interleaving, and …
which efficiently support scrambling, convolutional encoding, puncturing, interleaving, and …
Multiply-accumulate instruction set extension in a soft-core RISC Processor
Application Specific Instruction Set Processor (ASIP) design is known to offer optimum
performance and flexibility in a processor performance although with limited application …
performance and flexibility in a processor performance although with limited application …
Novel bit manipulation unit for communication digital signal processors
This paper proposes application-specific instructions and their bit manipulation unit (BMU),
which efficiently support scrambling, convolutional encoding, puncturing, and interleaving …
which efficiently support scrambling, convolutional encoding, puncturing, and interleaving …
Application-specific DSP architecture for fast Fourier transform
KL Heo, SM Cho, JH Lee… - … on Application-Specific …, 2003 - ieeexplore.ieee.org
We present ASDSP (application-specific digital signal processor) instructions and their
hardware architecture for high-speed FFT. The proposed instructions calculate a butterfly …
hardware architecture for high-speed FFT. The proposed instructions calculate a butterfly …
Three low power ASIP processor designs for communications, video, and audio applications
JS Kim, MH Sunwoo - … Conference on Design & Technology of …, 2007 - ieeexplore.ieee.org
This paper presents three Application Specific Instruction-set Processors (ASIP), Signal
Processor for OFDM Communication Systems (SPOCS), Video Specific Instruction-set …
Processor for OFDM Communication Systems (SPOCS), Video Specific Instruction-set …
[PDF][PDF] Low Power Pipelined Multiply-Accumulate Unit using Optimized Adders and Multipliers
S Cyril, DK Varugheese - International Journal of Advances in Engineering …, 2022 - ijaem.net
In the majority of the Digital signal processing (DSP) applications, the critical operations
usually involve many multiplications and/or accumulations. So for real time signal …
usually involve many multiplications and/or accumulations. So for real time signal …