Scalable hardware priority queue architectures for high-speed packet switches

SW Moon, J Rexford, KG Shin - IEEE Transactions on …, 2000 - ieeexplore.ieee.org
With effective packet-scheduling mechanisms, modern integrated networks can support the
diverse quality-of-service requirements of emerging applications. However, arbitrating …

Cost-function-based network selection strategy in integrated wireless and mobile networks

W Shen, QA Zeng - IEEE Transactions on Vehicular …, 2008 - ieeexplore.ieee.org
Wireless and mobile networks have experienced great success over the past few years.
However, any single type of wireless and mobile network cannot provide all types of …

Fast and scalable priority queue architecture for high-speed network switches

R Bhagwan, B Lin - … Nineteenth Annual Joint Conference of the …, 2000 - ieeexplore.ieee.org
In this paper, we present a fast and scalable pipelined priority queue architecture for use in
high-performance switches with support for fine grained quality of service (QoS) guarantees …

BMW Tree: Large-scale, High-throughput and Modular PIFO Implementation using Balanced Multi-Way Sorting Tree

R Yao, Z Zhang, G Fang, P Gao, S Liu, Y Fan… - Proceedings of the …, 2023 - dl.acm.org
Push-In-First-Out (PIFO) queue has been extensively studied as a programmable scheduler.
To achieve accurate, large-scale, and high-throughput PIFO implementation, we propose …

Parallel high-throughput limited search trellis decoder VLSI design

F Sun, T Zhang - IEEE Transactions on Very Large Scale …, 2005 - ieeexplore.ieee.org
Limited search trellis decoding algorithms have great potentials of realizing low power due
to their largely reduced computational complexity compared with the widely used Viterbi …

Priority queue schedulers with approximate sorting in output-buffered switches

J Liebeherr, DE Wrege - IEEE Journal on Selected Areas in …, 1999 - ieeexplore.ieee.org
All recently proposed packet-scheduling algorithms for output-buffered switches that support
quality-of-service (QoS) transmit packets in some priority order, eg, according to deadlines …

A maximum-likelihood soft-decision sequential decoding algorithm for binary convolutional codes

YS Han, PN Chen, HB Wu - IEEE Transactions on …, 2002 - ieeexplore.ieee.org
We present a trellis-based maximum-likelihood soft-decision sequential decoding algorithm
(MLSDA) for binary convolutional codes. Simulation results show that, for (2, 1, 6) and (2, 1 …

Scalable hardware earliest-deadline-first scheduler for ATM switching networks

BK Kim, KG Shin - Proceedings Real-Time Systems Symposium, 1997 - ieeexplore.ieee.org
A fast, scalable hardware earliest deadline first (EDF) link scheduler for ATM switching
network is developed. This EDF scheduler is a fast hardware solution suitable for real time …

A sequential decoder for linear block codes with a variable bias-term metric

V Sorokine, FR Kschischang - IEEE Transactions on …, 1998 - ieeexplore.ieee.org
A sequential decoder for linear block codes that performs maximum-likelihood soft-decision
decoding is described. The decoder uses a metric computed from a lower bound on the cost …

A fast systolic priority queue architecture for a flow-based Traffic Manager

I Benacer, FR Boyer, N Bélanger… - 2016 14th IEEE …, 2016 - ieeexplore.ieee.org
This paper presents a fast systolic priority queue architecture usable in a traffic manager.
The purpose of the traffic manager is to schedule the departure of packets on egress ports in …