Appl. No.: 11/945,387(57) 22) Filed: Nov. 27, 2007 Provided is a low-power clock gating
circuit using a Multi (22) Filed: OV. Af Threshold CMOS (MTCMOS) technique. The low …

G06F L/32(2006.01) G06F L/10(2006.01)(57) ABSTRACT G06F L/24(2006.01) A system
and method for automatically updating with hard (52) US Cl. ware clock tree settings on a …

The clock supply circuit of the present invention comprises a plurality of clock supply paths
and a clock gate circuit. The clock supply paths branch a clock signal and supply each of the …

US20080229266A1 - Design Structure for a Clock Distribution Network, Structure, and
Method for Providing Balanced Loading in Integrated Circuit Clock Trees - Google Patents …

BACKGROUND In integrated circuit (IC) design, one of the biggest chal lenges in the design
of high speed, high density application specific integrated circuits (ASICs) is the …

A clock gating system includes a clock divider, a first clock gating unit and a second clock
gating unit. The clock divider is employed to generate clock signals with different …

US20080229265A1 - Design Structure for a Clock Distribution Network, Structure, and
Method for Providing Balanced Loading in Integrated Circuit Clock Trees - Google Patents …

A computer-implemented method for generating a circuit design is provided according to
certain aspects. The method includes determining a gating efficiency of first gate-enable …

A circuit includes, in part, first and second sequential elements and a clock gating circuit.
The first sequential element has an enable terminal receiving a first enabling signal, a clock …

The present disclosure describes technologies and techniques for use by a data storage
controller—such as a non-volatile memory (NVM) controller—to adaptively and …