Effect of process variations in 3D global clock distribution networks
In three-dimensional (3D) integrated circuits, the effect of process variations on clock skew
differs from 2D circuits. The combined effect of inter-die and intra-die process variations on …
differs from 2D circuits. The combined effect of inter-die and intra-die process variations on …
Variation-tolerant and low-power clock network design for 3D ICs
X Zhao, S Mukhopadhyay… - 2011 IEEE 61st Electronic …, 2011 - ieeexplore.ieee.org
This paper studies the random characteristics of through-silicon-via (TSV)-based 3D clock
networks, taking into account both die-to-die and within-die process variations in clock …
networks, taking into account both die-to-die and within-die process variations in clock …
Resource allocation and design techniques of prebond testable 3-D clock tree
TY Kim, T Kim - IEEE Transactions on Computer-Aided Design …, 2012 - ieeexplore.ieee.org
In 3-D stacked integrated circuit (IC) manufacturing, for the acceptable high yield, it is
essential to stack only known good dies by testing the individual dies at the prebond stage …
essential to stack only known good dies by testing the individual dies at the prebond stage …
Timing uncertainty in 3-D clock trees due to process variations and power supply noise
Clock distribution networks are affected by different sources of variations. The resulting clock
uncertainty significantly affects the frequency of a circuit. To support this analysis, a statistical …
uncertainty significantly affects the frequency of a circuit. To support this analysis, a statistical …
Tier adaptive body biasing: a post-silicon tuning method to minimize clock skew variations in 3-D ICs
In this paper, we analyze the variability in a 3-D clock network designed with single and
multiple through-silicon vias and present a post-silicon tuning methodology, called tier …
multiple through-silicon vias and present a post-silicon tuning methodology, called tier …
Post silicon management of on-package variation induced 3D clock skew
TY Kim, TW Kim - JSTS: Journal of Semiconductor Technology and …, 2012 - koreascience.kr
Abstract A 3D stacked IC is made by multiple dies (possibly) with heterogeneous process
technologies. Therefore, die-to-die variation in 2D chips renders on-package variation (OPV) …
technologies. Therefore, die-to-die variation in 2D chips renders on-package variation (OPV) …
Skew variability in 3-D ICs with multiple clock domains
The effect of process variations on the clock skew in three dimensional (3-D) circuits with
multiple clock domains is investigated. In 3-D ICs, the combined effect of inter-die and intra …
multiple clock domains is investigated. In 3-D ICs, the combined effect of inter-die and intra …
Addressing process variations at the microarchitecture and system level
S Garg, D Marculescu - Foundations and Trends® in …, 2013 - nowpublishers.com
Technology scaling has resulted in an increasing magnitude of and sensitivity to
manufacturing process variations. This has led to the adoption of statistical design …
manufacturing process variations. This has led to the adoption of statistical design …
Clock network design techniques for 3D ICs
TY Kim, T Kim - … IEEE 54th International Midwest Symposium on …, 2011 - ieeexplore.ieee.org
3D die stacking is one of the most promising technology to overcome the traditional CMOS
scaling limitations and clock network design is an important design activity to guarantee right …
scaling limitations and clock network design is an important design activity to guarantee right …
Edge layer embedding algorithm for mitigating on-package variation in 3D clock tree synthesis
Abstract A 3D stacked IC is made of multiple dies possibly with heterogeneous process
technologies. Therefore, the die-to-die variation between the stacked dies creates on …
technologies. Therefore, the die-to-die variation between the stacked dies creates on …