Ark: Fully homomorphic encryption accelerator with runtime data generation and inter-operation key reuse

J Kim, G Lee, S Kim, G Sohn, M Rhu… - 2022 55th IEEE/ACM …, 2022 - ieeexplore.ieee.org
Homomorphic Encryption (HE) is one of the most promising post-quantum cryptographic
schemes that enable privacy-preserving computation on servers. However, noise …

[图书][B] Embedded system design: embedded systems foundations of cyber-physical systems, and the internet of things

P Marwedel - 2021 - library.oapen.org
A unique feature of this open access textbook is to provide a comprehensive introduction to
the fundamental knowledge in embedded systems, with applications in cyber-physical …

Clock rate versus IPC: The end of the road for conventional microarchitectures

V Agarwal, MS Hrishikesh, SW Keckler… - Proceedings of the 27th …, 2000 - dl.acm.org
The doubling of microprocessor performance every three years has been the result of two
factors: more transistors per chip and superlinear scali ng of the processor clock with …

Smart memories: A modular reconfigurable architecture

K Mai, T Paaske, N Jayasena, R Ho, WJ Dally… - Proceedings of the 27th …, 2000 - dl.acm.org
Trends in VLSI technology scaling demand that future computing devices be narrowly
focused to achieve high performance and high efficiency, yet also target the high volumes …

Imagine: Media processing with streams

B Khailany, WJ Dally, UJ Kapasi, P Mattson… - IEEE micro, 2001 - ieeexplore.ieee.org
The power-efficient Imagine stream processor achieves performance densities comparable
to those of special-purpose embedded processors. Executing programs mapped to streams …

The Imagine stream processor

UJ Kapasi, WJ Dally, S Rixner… - … on Computer Design …, 2002 - ieeexplore.ieee.org
The Imagine Stream Processor is a single-chip programmable media processor with 48
parallel ALUs. At 400 MHz, this translates to a peak arithmetic rate of 16 GFLOPS on single …

SODA: A low-power architecture for software radio

Y Lin, H Lee, M Woh, Y Harel, S Mahlke… - ACM SIGARCH …, 2006 - dl.acm.org
The physical layer of most wireless protocols is traditionally implemented in custom
hardware to satisfy the heavy computational requirements while keeping power …

Multiple-banked register file architectures

JL Cruz, A González, M Valero… - Proceedings of the 27th …, 2000 - dl.acm.org
The register file access time is one of the critical delays in current superscalar processors. Its
impact on processor performance is likely to increase in future processor generations, as …

Reducing the complexity of the register file in dynamic superscalar processors

R Balasubramonian, S Dwarkadas… - … . 34th ACM/IEEE …, 2001 - ieeexplore.ieee.org
Dynamic superscalar processors execute multiple instructions out-of-order by looking for
independent operations within a large window. The number of physical registers within the …

Efficient multi-ported memories for FPGAs

CE LaForest, JG Steffan - Proceedings of the 18th annual ACM/SIGDA …, 2010 - dl.acm.org
Multi-ported memories are challenging to implement with FPGAs since the provided block
RAMs typically have only two ports. We present a thorough exploration of the design space …