As very large-scale integration technology shrinks to fewer tracks per standard cell, eg, from
10 to 7.5-track libraries (and lesser for 7 nm), there has been a rapid increase in the usage …

Utilizing multibit flip-flops (MBFFs) is one of the most effective power optimization techniques
in modern nanometer integrated circuit design. Most of the previous works apply MBFFs …

Placement consists of three stages: global placement, legalization, and detailed placement
(DP). Recently, most research works have concentrated on improving global placement and …

Clock network power reduction is critical in modern SoC designs. Application of flop trays
(ie, multi-bit flip-flops) can significantly reduce the number of sinks in a clock network, and …

Utilizing multi-bit flip-flops (MBFFs) is one of the most effective power optimization
techniques in modern nanometer integrated circuit (IC) design. Most of the previous work …

Multibit register (MBR) composition is an effective and proven method for clock tree power
reduction. The proposed MBR composition follows a balanced restructuring approach that is …

Multi-bit flip-flops (MBFFs) are often used to reduce the number of clock sinks, resulting in a
low-power design. A traditional MBFF is composed of individual FFs of uniform driving …

Clock network should be optimized to reduce clock power dissipation. The power efficient
clock network can be constructed by multibit flip-flop generation and gated clock tree aware …

With the continued scaling to emerging technology nodes, modern circuit designs in
nanometer era introduce many strict or even unprecedented design constraints and …

Applying clock gates (CGs) and multi-bit flip-flops (MBFFs) are two of the most effective
techniques for low power clock network design. Some previous works had proposed to …