2. Description of the Related Art Conventional integrated circuits incorporate planar field
effect transistors (FETs) in which current flows through a semiconducting channel between a …

FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that
extends out from the surface of a doped drain formed in a silicon substrate. The vertical …

(57) ABSTRACT A method of forming a vertical fin field effect transistor (vertical finFET) with
a self-aligned bottom source/drain, including forming a doped layer on a substrate, forming …

Methods are provided for manufacturing semiconductor devices include forming a first fin
protruding on a substrate and extending in a first direction; forming first and second …

Source and drain formation techniques are disclosed herein for fin-like field effect transistors
(FinFETs). An exemplary method for forming epitaxial source/drain features for a FinFET …

GAA FET is intended to meet design and performance criteria for the 7 nm technology
generation. In some embodi ments, electrical contacts to the drain and gate terminals of the …

(57) ABSTRACT A method of forming a semiconductor device that includes forming an in-
situ doped semiconductor material on a semi conductor Substrate, and forming fin structures …

(57) ABSTRACT A vertical tunneling FET (TFET) provides low-power, high speed Switching
performance for transistors having critical (51) Int. Cl dimensions below 7 nm. The vertical …

(57) ABSTRACT A method includes forming Shallow Trench Isolation (STI) regions in a
semiconductor substrate and a semiconductor strip between the STI regions. The method …

Thus, in one aspect, the present invention relates to a method of making a semiconductor
device, comprising pro viding a silicon-on-insulator Substrate having a first insulat ing layer …