A survey on design approaches to circumvent permanent faults in networks-on-chip

S Werner, J Navaridas, M Luján - ACM Computing Surveys (CSUR), 2016 - dl.acm.org
Increasing fault rates in current and future technology nodes coupled with on-chip
components in the hundreds calls for robust and fault-tolerant Network-on-Chip (NoC) …

A survey on undirected circulant graphs

EA Monakhova - Discrete Mathematics, Algorithms and Applications, 2012 - World Scientific
Circulant graphs have been extensively investigated over the past 30 years because of their
broad application to different fields of theory and practice. Two known surveys on circulant …

Modeling toroidal networks with the Gaussian integers

C Martínez, R Beivide, E Stafford… - IEEE Transactions …, 2008 - ieeexplore.ieee.org
In this paper we consider a broad family of toroidal networks, denoted as Gaussian
networks, which include many previously proposed and used topologies. We will define …

Twisted torus topologies for enhanced interconnection networks

JM Camara, M Moreto, E Vallejo… - … on Parallel and …, 2010 - ieeexplore.ieee.org
Many current parallel computers are built around a torus interconnection network. Machines
from Cray, HP, and IBM, among others, make use of this topology. In terms of topological …

Cluster-fault tolerant routing in a torus

A Bossard, K Kaneko - Sensors, 2020 - mdpi.com
The number of Internet-connected devices grows very rapidly, with even fears of running out
of available IP addresses. It is clear that the number of sensors follows this trend, thus …

Dav: A humanoid robot platform for autonomous mental development

JD Han, SQ Zeng, KY Tham… - … on Development and …, 2002 - ieeexplore.ieee.org
A humanoid robot, called Dav, was developed at Michigan State University as a testbed for
experimental investigations into autonomous mental development. This general-purpose …

Optimal low-latency network topologies for cluster performance enhancement

Y Deng, M Guo, AF Ramos, X Huang, Z Xu… - The Journal of …, 2020 - Springer
We propose that clusters interconnected with network topologies having minimal mean path
length will increase their processing speeds. We approach our heuristic by constructing …

Dense Gaussian networks: Suitable topologies for on-chip multiprocessors

C Martínez, E Vallejo, R Beivide, C Izu… - International Journal of …, 2006 - Springer
This paper explores the suitability of dense circulant graphs of degree four for the design of
on-chip interconnection networks. Networks based on these graphs reduce the Torus …

Interlacing bypass rings to torus networks for more efficient networks

P Zhang, R Powell, Y Deng - IEEE Transactions on Parallel …, 2010 - ieeexplore.ieee.org
We introduce a new technique for generating more efficient networks by systematically
interlacing bypass rings to torus networks (iBT networks). The resulting network can improve …

Performance, cost, and energy evaluation of fat h-tree: A cost-efficient tree-based on-chip network

H Matsutani, M Koibuchi… - 2007 IEEE International …, 2007 - ieeexplore.ieee.org
Fat H-Tree is a novel tree-based interconnection network providing a torus structure, which
is formed by combining two folded H-Tree networks, and is an attractive alternative to tree …