A method and apparatus of a power gating technique to reduce power in functional and test
modes are disclosed. In one embodiment, a method includes separating a power domain of …

BACKGROUND It is known to provide data processing systems which con tain a number of
state retention circuits configured to hold respective state values at respective nodes of the …

A semiconductor device according to an embodiment includes a plurality of scan chains
each including a retention flip-flop, and a control section configured to perform restoration of …

An integrated circuit (IC) includes a flip-flop that stores data when the IC is in built-in self-test
(BIST) mode. The flip-flop includes a master latch connected to a slave latch, which in turn is …

A data processing apparatus is provided with state retention circuits into which state values
are saved from nodes within the data processing circuitry when entering a sleep mode from …

In a circuit adapted for scan testing, a first set of connections configures the circuit elements
into power domains with separate power-level controls, and a second set of connections …

Embodiments relate to methodologies for applying multibit cell merging to functional shift
registers, thereby saving area, reducing scan-wirelength, saving power and reducing wiring …

An electronic circuit includes transmit-side circuitry and receive-side circuitry. The transmit-
side circuitry belongs to a first domain of the circuit and is configured to transmit a data …

Determine pattern faults for state-retention cells retention-cell values in the retention element
during power variations in the power domain; determining one or more pattern faults for …

US9625526B2 - Method and apparatus for scan chain data management - Google Patents
US9625526B2 - Method and apparatus for scan chain data management - Google Patents …