Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods

RJ Mears, H Takeuchi - US Patent 9,899,479, 2018 - Google Patents
(57) ABSTRACT A semiconductor device may include a semiconductor sub strate, and a
plurality of field effect transistors (FETs) on the semiconductor substrate. Each FET may …

Semiconductor devices with enhanced deterministic doping and related methods

RJ Mears - US Patent 10,170,560, 2019 - Google Patents
(57) ABSTRACT A method for making a semiconductor device may include forming a
plurality of stacked groups of layers on a semi conductor substrate, with each group of layers …

Semiconductor device including a superlattice and replacement metal gate structure and related methods

RJ Mears, TJK Liu, H Takeuchi - US Patent 10,084,045, 2018 - Google Patents
A semiconductor device may include a substrate having a channel recess therein, a plurality
of spaced apart shallow trench isolation (STI) regions in the substrate, and source and drain …

Semiconductor device including a superlattice and replacement metal gate structure and related methods

RJ Mears, TJK Liu, H Takeuchi - US Patent 9,722,046, 2017 - Google Patents
(57) ABSTRACT A semiconductor device may include a substrate having a channel recess
therein, a plurality of spaced apart shallow trench isolation (STI) regions in the Substrate …

Method for making enhanced semiconductor structures in single wafer processing chamber with desired uniformity control

RJ Mears, N Cody, RJ Stephenson - US Patent 9,721,790, 2017 - Google Patents
US9721790B2 - Method for making enhanced semiconductor structures in single wafer
processing chamber with desired uniformity control - Google Patents US9721790B2 - Method …

Methods for making a semiconductor device including atomic layer structures using N2O as an oxygen source

R Stephenson, N Cody - US Patent 9,558,939, 2017 - Google Patents
A method for making a semiconductor device may include forming a plurality of spaced apart
structures on a semiconductor substrate within a semiconductor processing chamber, with …

Vertical semiconductor devices including superlattice punch through stop layer and related methods

R Mears, H Takeuchi, E Trautmann - US Patent 9,972,685, 2018 - Google Patents
(57) ABSTRACT A semiconductor device may include a substrate, and a plurality of fins
spaced apart on the substrate. Each of the fins may include a lower semiconductor fin …

Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methods

RJ Mears, H Takeuchi - US Patent 9,941,359, 2018 - Google Patents
(57) ABSTRACT A semiconductor device may include a semiconductor sub strate and first
transistors having a first operating voltage. Each first transistor may include a first channel …

Semiconductor device with a vertical MOSFET including a superlattice and related methods

KV Rao - US Patent 7,781,827, 2010 - Google Patents
A semiconductor device may include at least one vertical Metal Oxide Semiconductor Field
Effect Transistor (MOSFET) on a substrate. The vertical MOSFET may include at least one …

Semiconductor devices with enhanced deterministic doping and related methods

RJ Mears - US Patent 9,716,147, 2017 - Google Patents
A method for making a semiconductor device may include forming a plurality of stacked
groups of layers on a semiconductor substrate, with each group of layers including a …